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a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=11jpJ+2AJLykVH7TWNShFOVqaSyMY1EvV87FLFMToFI=; b=ablUrsOsNvXF2C4cTeKSmwvs6e7FpoczbN5ByVFyftnE4/RFGrPO3g8vF98IiZUVzK/DhjseLu/eSP0x9/Bvl7CWIr9+zs0WFisW0cT+jTQF+dKYCMiY3HBZHHVx+8DMwVOyjKNllPROYdJluOYD9iLWGLWcLABy6XzZZMRkKmA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jayachandran.Nair@cavium.com; Received: from jc-sabre.caveonetworks.com (50.233.148.156) by DM2PR0701MB1068.namprd07.prod.outlook.com (2a01:111:e400:2472::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.407.7; Fri, 19 Jan 2018 12:23:07 +0000 From: Jayachandran C To: Will Deacon , Jon Masters Cc: marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org, Jayachandran C Subject: [PATCH v3 2/2] arm64: Turn on KPTI only on CPUs that need it Date: Fri, 19 Jan 2018 04:22:48 -0800 Message-Id: <1516364568-95577-2-git-send-email-jnair@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> References: <20180118135354.GB20783@arm.com> <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: DM5PR2001CA0021.namprd20.prod.outlook.com (2603:10b6:4:16::31) To DM2PR0701MB1068.namprd07.prod.outlook.com (2a01:111:e400:2472::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 661b13ce-692a-480b-4b33-08d55f3765ab X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(4534125)(4602075)(4627221)(201703031133081)(201702281549075)(5600026)(4604075)(2017052603307)(7153060)(7193020);SRVR:DM2PR0701MB1068; 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These CPUs are not vulnerable to CVE-2017-5754 and do not need KPTI when KASLR is off. Signed-off-by: Jayachandran C --- arch/arm64/kernel/cpufeature.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 647d44b..fb698ca 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -866,6 +866,13 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) return true; + /* Don't force KPTI for CPUs that are not vulnerable */ + switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { + case MIDR_CAVIUM_THUNDERX2: + case MIDR_BRCM_VULCAN: + return false; + } + /* Defer to CPU feature registers */ return !cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV3_SHIFT); -- 2.7.4