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[209.132.180.67]) by mx.google.com with ESMTP id b96-v6si1611879pli.48.2018.01.20.09.17.17; Sat, 20 Jan 2018 09:17:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@lechnology.com header.s=default header.b=TjsXyLBr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756528AbeATRQl (ORCPT + 99 others); Sat, 20 Jan 2018 12:16:41 -0500 Received: from vern.gendns.com ([206.190.152.46]:42588 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756483AbeATRPJ (ORCPT ); Sat, 20 Jan 2018 12:15:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=0+2cnkFzgQfpNwXNimEGh+cDhZSYexiIijq2GQ8A8Gs=; b=TjsXyLBrgg4qIoUM/kJ+yZ88d KgB4M/mdCDREUoaBTDwo7HXdDbJQ45NJDFXahhVCSXKTs4Q83VccRhBO3lUlQUQvgICOPqU92AUSU p754SPg0fIo1LghzGKKYe5Y+FA1cESIROmdkH5ndNrjJgixjN123vyaNa/vjkuQ5TaZWmnh7VZN/5 e0Gz2XYJ5rk+f8xi0vM8mmIcKTjR3gIiwFLT9QhZtrSRE9RAKqr/37yeOp75r4WH9srzYUm2ybHtr j3krDugB2LzjoJzvvy2bs7S9Vn1os2WugvBbijO3i6IqTcnQJpVONXVdDHDBuuixaNbUCC62gmTYk Frm+gXx2w==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53590 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89_1) (envelope-from ) id 1ecwj1-00059q-3Y; Sat, 20 Jan 2018 12:14:39 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v6 07/41] clk: davinci: Add platform information for TI DM644x PLL Date: Sat, 20 Jan 2018 11:13:46 -0600 Message-Id: <1516468460-4908-8-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516468460-4908-1-git-send-email-david@lechnology.com> References: <1516468460-4908-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds platform-specific declarations for the PLL clocks on TI DM644x based systems. Signed-off-by: David Lechner --- v6 changes: - Added dm644x_pll{1,2}_info with controller-specific information - Add empty lines between function calls drivers/clk/davinci/Makefile | 1 + drivers/clk/davinci/pll-dm644x.c | 67 ++++++++++++++++++++++++++++++++++++++++ include/linux/clk/davinci.h | 1 + 3 files changed, 69 insertions(+) create mode 100644 drivers/clk/davinci/pll-dm644x.c diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile index 353aa02..59d8ab6 100644 --- a/drivers/clk/davinci/Makefile +++ b/drivers/clk/davinci/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o +obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o endif diff --git a/drivers/clk/davinci/pll-dm644x.c b/drivers/clk/davinci/pll-dm644x.c new file mode 100644 index 0000000..0c9b80f --- /dev/null +++ b/drivers/clk/davinci/pll-dm644x.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock descriptions for TI DM644X + * + * Copyright (C) 2018 David Lechner + */ + +#include +#include +#include + +#include "pll.h" + +static const struct davinci_pll_clk_info dm644x_pll1_info __initconst = { + .name = "pll1", + .pllm_mask = GENMASK(4, 0), + .pllm_min = 1, + .pllm_max = 32, + .pllout_min_rate = 400000000, + .pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */ + .flags = PLL_HAS_OSCIN | PLL_HAS_POSTDIV, +}; + +static const struct davinci_pll_sysclk_info dm644x_pll1_sysclk_info[] __initconst = { + SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV), + SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV), + SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV), + SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV), + { } +}; + +static const struct davinci_pll_clk_info dm644x_pll2_info __initconst = { + .name = "pll2", + .pllm_mask = GENMASK(4, 0), + .pllm_min = 1, + .pllm_max = 32, + .pllout_min_rate = 400000000, + .pllout_max_rate = 900000000, + .flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV, +}; + +static const struct davinci_pll_sysclk_info dm644x_pll2_sysclk_info[] __initconst = { + SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0), + SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0), + { } +}; + +void __init dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2) +{ + const struct davinci_pll_sysclk_info *info; + + davinci_pll_clk_register(&dm644x_pll1_info, "ref_clk", pll1); + + for (info = dm644x_pll1_sysclk_info; info->name; info++) + davinci_pll_sysclk_register(info, pll1); + + davinci_pll_auxclk_register("pll1_auxclk", pll1); + + davinci_pll_sysclkbp_clk_register("pll1_sysclkbp", pll1); + + davinci_pll_clk_register(&dm644x_pll2_info, "oscin", pll2); + + for (info = dm644x_pll2_sysclk_info; info->name; info++) + davinci_pll_sysclk_register(info, pll2); + + davinci_pll_sysclkbp_clk_register("pll2_sysclkbp", pll2); +} diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h index 5bf60a7..535990a 100644 --- a/include/linux/clk/davinci.h +++ b/include/linux/clk/davinci.h @@ -13,5 +13,6 @@ void da830_pll_clk_init(void __iomem *pll); void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1); void dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2); void dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2); +void dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2); #endif /* __LINUX_CLK_DAVINCI_H__ */ -- 2.7.4