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[209.132.180.67]) by mx.google.com with ESMTP id b2si10502034pgc.37.2018.01.20.09.20.45; Sat, 20 Jan 2018 09:20:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@lechnology.com header.s=default header.b=kO+iP3Nj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756673AbeATRUA (ORCPT + 99 others); Sat, 20 Jan 2018 12:20:00 -0500 Received: from vern.gendns.com ([206.190.152.46]:42771 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756624AbeATRPj (ORCPT ); Sat, 20 Jan 2018 12:15:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=4kHVZPl2pp0o6VK6DRB7Qd9qjAB5AJmt4N/QK6aetg4=; b=kO+iP3NjT2XHEkfffJzQVIYPc w2x/jkIm/Yj5TX4hgZ2QYmhaQ8wuc2H4uMXPUVysbYGL7b42MCm9cbj0jh6HRwaXRilKHKesOBbR7 G1+zR4iosoScYQ5WaHUT2BGWoyDxBoWNu4N2zHIipmNLVJYLkxXDnuTnFtNSCF4B1AlynlkDeMAss r1xuIOhvC4r8l7PAp0U90tRiH9LqL0+ajfyXV+t4LNxpdeBikneR/TaPcwFJ1RQwqONC6EtaXTxVH Dg1WfV3r/fxhaaL7xr0+L2RQz8/oBCUq2TfVtWCJxsRTkMybB+VYVE883dlauLLIa8RStGcNBOsKF vxrEcgImA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53590 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89_1) (envelope-from ) id 1ecwjU-00059q-D2; Sat, 20 Jan 2018 12:15:08 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v6 22/41] ARM: dm355: add new clock init using common clock framework Date: Sat, 20 Jan 2018 11:14:01 -0600 Message-Id: <1516468460-4908-23-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516468460-4908-1-git-send-email-david@lechnology.com> References: <1516468460-4908-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the new board-specific clock init in mach-davinci/dm355.c using the new common clock framework drivers. The #ifdefs are needed to prevent compile errors until the entire ARCH_DAVINCI is converted. Also clean up the #includes since we are adding some here. Signed-off-by: David Lechner --- v6 changes: - add blank lines between function calls arch/arm/mach-davinci/dm355.c | 49 +++++++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index f294804..2c19739 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -8,31 +8,37 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include +#include #include -#include -#include +#include +#include #include #include -#include +#include #include #include #include +#include +#include +#include #include +#include #include -#include "psc.h" -#include #include -#include +#include #include -#include +#include +#include "asp.h" #include "davinci.h" -#include "clock.h" #include "mux.h" -#include "asp.h" + +#ifndef CONFIG_COMMON_CLK +#include "clock.h" +#include "psc.h" +#endif #define DM355_UART2_BASE (IO_PHYS + 0x206000) #define DM355_OSD_BASE (IO_PHYS + 0x70200) @@ -43,6 +49,7 @@ */ #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ +#ifndef CONFIG_COMMON_CLK static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -382,7 +389,7 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "usb", &usb_clk), CLK(NULL, NULL, NULL), }; - +#endif /*----------------------------------------------------------------------*/ static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); @@ -1046,7 +1053,27 @@ void __init dm355_init(void) void __init dm355_init_time(void) { +#ifdef CONFIG_COMMON_CLK + void __iomem *pll1, *pll2, *psc; + + pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_4K); + pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_4K); + psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); + + dm355_pll_clk_init(pll1, pll2); + + dm355_psc_clk_init(psc); + + /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */ + clk_register_fixed_factor(NULL, "clkout1", "pll1_aux_clk", 0, 1, 1); + clk_register_fixed_factor(NULL, "clkout2", "pll1_sysclkbp", 0, 1, 1); + /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */ + clk_register_fixed_factor(NULL, "clkout3", "pll2_sysclkbp", 0, 1, 1); +#else davinci_clk_init(dm355_clks); +#endif davinci_timer_init(); } -- 2.7.4