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From:   Steven Noonan <steven@uplinklabs.net>
Date:   Sat, 20 Jan 2018 13:51:14 -0800
Message-ID: <CAKbGBLi3vixq2aMzmhLY2NysWqc8qo7BoFysFcsm9TEdQdCErA@mail.gmail.com>
Subject: Re: [PATCH 1/4] x86/cpufeatures: Add Intel feature bits for
 Speculation Control
To:     David Woodhouse <dwmw@amazon.co.uk>
Cc:     Arjan van de Ven <arjan@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>, karahmed@amazon.de,
        Linux-X86 <x86@kernel.org>,
        Linux Kernel mailing List <linux-kernel@vger.kernel.org>,
        tim.c.chen@linux.intel.com, Borislav Petkov <bp@alien8.de>,
        Peter Zijlstra <peterz@infradead.org>,
        Paolo Bonzini <pbonzini@redhat.com>, ak@linux.intel.com,
        Linus Torvalds <torvalds@linux-foundation.org>,
        gregkh@linux-foundation.org
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Sender: linux-kernel-owner@vger.kernel.org
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On Sat, Jan 20, 2018 at 4:03 AM, David Woodhouse <dwmw@amazon.co.uk> wrote:
> Add three feature bits exposed by new microcode on Intel CPUs for
> speculation control. We would now be up to five bits in CPUID(7).RDX
> so take them out of the 'scattered' features and make a proper word
> for them instead.
>
> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
> ---
>  arch/x86/include/asm/cpufeature.h        |  7 +++++--
>  arch/x86/include/asm/cpufeatures.h       | 12 +++++++++---
>  arch/x86/include/asm/disabled-features.h |  3 ++-
>  arch/x86/include/asm/required-features.h |  3 ++-
>  arch/x86/kernel/cpu/common.c             |  1 +
>  arch/x86/kernel/cpu/scattered.c          |  2 --
>  6 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index ea9a7dd..70eddb3 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -29,6 +29,7 @@ enum cpuid_leafs
>         CPUID_8000_000A_EDX,
>         CPUID_7_ECX,
>         CPUID_8000_0007_EBX,
> +       CPUID_7_EDX,
>  };
>
>  #ifdef CONFIG_X86_FEATURE_NAMES
> @@ -79,8 +80,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
>            CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) ||    \
>            CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||    \
>            CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||    \
> +          CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||    \
>            REQUIRED_MASK_CHECK                                    ||    \
> -          BUILD_BUG_ON_ZERO(NCAPINTS != 18))
> +          BUILD_BUG_ON_ZERO(NCAPINTS != 19))
>
>  #define DISABLED_MASK_BIT_SET(feature_bit)                             \
>          ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||    \
> @@ -101,8 +103,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
>            CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) ||    \
>            CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||    \
>            CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||    \
> +          CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||    \
>            DISABLED_MASK_CHECK                                    ||    \
> -          BUILD_BUG_ON_ZERO(NCAPINTS != 18))
> +          BUILD_BUG_ON_ZERO(NCAPINTS != 19))
>
>  #define cpu_has(c, bit)                                                        \
>         (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :  \
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 25b9375..adebdaa 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -13,7 +13,7 @@
>  /*
>   * Defines x86 CPU feature bits
>   */
> -#define NCAPINTS                       18         /* N 32-bit words worth of info */
> +#define NCAPINTS                       19         /* N 32-bit words worth of info */
>  #define NBUGINTS                       1          /* N 32-bit bug flags */
>
>  /*
> @@ -206,8 +206,6 @@
>  #define X86_FEATURE_RETPOLINE          ( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
>  #define X86_FEATURE_RETPOLINE_AMD      ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
>  #define X86_FEATURE_INTEL_PPIN         ( 7*32+14) /* Intel Processor Inventory Number */
> -#define X86_FEATURE_AVX512_4VNNIW      ( 7*32+16) /* AVX-512 Neural Network Instructions */
> -#define X86_FEATURE_AVX512_4FMAPS      ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
>
>  #define X86_FEATURE_MBA                        ( 7*32+18) /* Memory Bandwidth Allocation */
>  #define X86_FEATURE_RSB_CTXSW          ( 7*32+19) /* Fill RSB on context switches */
> @@ -319,6 +317,14 @@
>  #define X86_FEATURE_SUCCOR             (17*32+ 1) /* Uncorrectable error containment and recovery */
>  #define X86_FEATURE_SMCA               (17*32+ 3) /* Scalable MCA */
>
> +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
> +#define X86_FEATURE_AVX512_4VNNIW      (18*32+ 2) /* AVX-512 Neural Network Instructions */
> +#define X86_FEATURE_AVX512_4FMAPS      (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
> +#define X86_FEATURE_SPEC_CTRL          (18*32+26) /* Speculation Control (IBRS + IBPB) */
> +#define X86_FEATURE_STIPB              (18*32+27) /* Speculation Control with STIPB (Intel) */

Is this correct? I thought the acronym was "STIBP", i.e.
"Single-Thread Indrect Branch Prediction"? If so, then you've got the
B and P swapped.

> +#define X86_FEATURE_ARCH_CAPABILITIES  (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
> +
> +
>  /*
>   * BUG word(s)
>   */
> diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
> index e428e16..c6a3af1 100644
> --- a/arch/x86/include/asm/disabled-features.h
> +++ b/arch/x86/include/asm/disabled-features.h
> @@ -71,6 +71,7 @@
>  #define DISABLED_MASK15        0
>  #define DISABLED_MASK16        (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57)
>  #define DISABLED_MASK17        0
> -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
> +#define DISABLED_MASK18        0
> +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
>
>  #endif /* _ASM_X86_DISABLED_FEATURES_H */
> diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
> index d91ba04..fb3a6de 100644
> --- a/arch/x86/include/asm/required-features.h
> +++ b/arch/x86/include/asm/required-features.h
> @@ -106,6 +106,7 @@
>  #define REQUIRED_MASK15        0
>  #define REQUIRED_MASK16        (NEED_LA57)
>  #define REQUIRED_MASK17        0
> -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
> +#define REQUIRED_MASK18        0
> +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
>
>  #endif /* _ASM_X86_REQUIRED_FEATURES_H */
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 372ba3f..e5d66e9 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -745,6 +745,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
>                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
>                 c->x86_capability[CPUID_7_0_EBX] = ebx;
>                 c->x86_capability[CPUID_7_ECX] = ecx;
> +               c->x86_capability[CPUID_7_EDX] = edx;
>         }
>
>         /* Extended state features: level 0x0000000d */
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index d0e6976..df11f5d 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -21,8 +21,6 @@ struct cpuid_bit {
>  static const struct cpuid_bit cpuid_bits[] = {
>         { X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
>         { X86_FEATURE_EPB,              CPUID_ECX,  3, 0x00000006, 0 },
> -       { X86_FEATURE_AVX512_4VNNIW,    CPUID_EDX,  2, 0x00000007, 0 },
> -       { X86_FEATURE_AVX512_4FMAPS,    CPUID_EDX,  3, 0x00000007, 0 },
>         { X86_FEATURE_CAT_L3,           CPUID_EBX,  1, 0x00000010, 0 },
>         { X86_FEATURE_CAT_L2,           CPUID_EBX,  2, 0x00000010, 0 },
>         { X86_FEATURE_CDP_L3,           CPUID_ECX,  2, 0x00000010, 1 },
> --
> 2.7.4
>