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[209.132.180.67]) by mx.google.com with ESMTP id b15si1541219pfe.31.2018.01.21.01.53.25; Sun, 21 Jan 2018 01:53:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=um+FXYG8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751076AbeAUJt0 (ORCPT + 99 others); Sun, 21 Jan 2018 04:49:26 -0500 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:56244 "EHLO smtp-fw-33001.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750911AbeAUJtY (ORCPT ); Sun, 21 Jan 2018 04:49:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1516528164; x=1548064164; h=from:to:subject:date:message-id; bh=Hy6Z3ssly/69fZB1FWFAVIRyp8kXql76WbQb2qoQiIU=; b=um+FXYG8LjEpn3gnx9wdNkF3bHIbFxtgIVx6fvEuBG373iHJETDfysUs N+RCLvzlKbVXC4KAVT/qB7orIWBRqI7LiM2aGuWQu9ASPIxPZKfBXa+xD 4rvRzEc+8+aWZiviOSFHlKQ4EGAFBSLvQPLtV/znAIXDRn7irIx0IWEel c=; X-IronPort-AV: E=Sophos;i="5.46,390,1511827200"; d="scan'208";a="716493962" Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-2a-6e2fc477.us-west-2.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 21 Jan 2018 09:49:23 +0000 Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-6e2fc477.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w0L9nIhb103311 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 21 Jan 2018 09:49:19 GMT Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (localhost [127.0.0.1]) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w0L9nH56010278; Sun, 21 Jan 2018 09:49:17 GMT Received: (from dwmw@localhost) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Submit) id w0L9nFSc010273; Sun, 21 Jan 2018 09:49:15 GMT From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: [PATCH v2 0/8] Speculation Control feature support, IBPB Date: Sun, 21 Jan 2018 09:49:01 +0000 Message-Id: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Combining my previous patchset for purely adding the feature and MSR definitions, with the first four patches that Karim sent out which were purely about enabling IBPB. This gives us a full retpoline-based mitigation for Spectre variant 2, and the IBRS option can come later. I expect further discussion of the final patch to tweak precisely when we use IBPB in context switch. --- v2: Fix STIPB/STIBP typo Fix error in AMD CPUID bit definition (0x8000_0008 EBX[12]) Ashok Raj (1): x86/kvm: Add IBPB support David Woodhouse (4): x86/cpufeatures: Add Intel feature bits for Speculation Control x86/cpufeatures: Add AMD feature bits for Prediction Command x86/msr: Add definitions for new speculation control MSRs x86/pti: Do not enable PTI on fixed Intel processors Thomas Gleixner (2): x86/speculation: Add basic support for IBPB x86/speculation: Use Indirect Branch Prediction Barrier in context switch Tim Chen (1): x86/mm: Only flush indirect branches when switching into non dumpable process arch/x86/include/asm/cpufeature.h | 7 +++++-- arch/x86/include/asm/cpufeatures.h | 14 +++++++++++--- arch/x86/include/asm/disabled-features.h | 3 ++- arch/x86/include/asm/msr-index.h | 11 +++++++++++ arch/x86/include/asm/nospec-branch.h | 16 ++++++++++++++++ arch/x86/include/asm/required-features.h | 3 ++- arch/x86/kernel/cpu/bugs.c | 7 +++++++ arch/x86/kernel/cpu/common.c | 10 ++++++++-- arch/x86/kernel/cpu/scattered.c | 3 +-- arch/x86/kvm/svm.c | 14 ++++++++++++++ arch/x86/kvm/vmx.c | 11 +++++++++++ arch/x86/mm/tlb.c | 21 ++++++++++++++++++++- 12 files changed, 108 insertions(+), 12 deletions(-) -- 2.7.4