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Date:   Sun, 21 Jan 2018 12:22:47 -0000
Subject: Re: [PATCH 2/4] x86/cpufeatures: Add AMD feature bits for Prediction
 Command
From:   "David Woodhouse" <dwmw2@infradead.org>
To:     "Borislav Petkov" <bp@alien8.de>
Cc:     "David Woodhouse" <dwmw@amazon.co.uk>,
        "Tom Lendacky" <thomas.lendacky@amd.com>, arjan@linux.intel.com,
        tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org,
        linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com,
        peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com,
        torvalds@linux-foundation.org, gregkh@linux-foundation.org
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> On Sat, Jan 20, 2018 at 12:03:31PM +0000, David Woodhouse wrote:
>> AMD doesn't implement the Speculation Control MSR that Intel does, but
>> the Prediction Control MSR does exist and is advertised by a separate
>> CPUID bit. Add support for that.
>>
>> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
>> ---
>>  arch/x86/include/asm/cpufeatures.h | 1 +
>>  arch/x86/kernel/cpu/scattered.c    | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h
>> b/arch/x86/include/asm/cpufeatures.h
>> index adebdaa..624d978 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -207,6 +207,7 @@
>>  #define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* AMD Retpoline
>> mitigation for Spectre variant 2 */
>>  #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory
>> Number */
>>
>> +#define X86_FEATURE_AMD_PRED_CMD	( 7*32+17) /* Prediction Command MSR
>> (AMD) */
>
> Right, so this bit I've seen being called differently. Tom, can you
> clarify pls?

Yeah, that's fat-fingered in a cut/paste in refactoring. Fixed in what I
posted this morning. I would like to see public docs with it though...
Tom?

-- 
dwmw2