Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Message-ID: <2100854a140a0758f4e0c70e80e22701.squirrel@twosheds.infradead.org>
In-Reply-To: <ae7102d6-4df8-63eb-2e1e-c7cee69fea9e@suse.cz>
References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk>
    <1516528149-9370-4-git-send-email-dwmw@amazon.co.uk>
    <ae7102d6-4df8-63eb-2e1e-c7cee69fea9e@suse.cz>
Date:   Sun, 21 Jan 2018 13:27:30 -0000
Subject: Re: [PATCH v2 3/8] x86/msr: Add definitions for new speculation
 control MSRs
From:   "David Woodhouse" <dwmw2@infradead.org>
To:     "Jiri Slaby" <jslaby@suse.cz>
Cc:     "David Woodhouse" <dwmw@amazon.co.uk>, arjan@linux.intel.com,
        tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org,
        linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com,
        bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com,
        ak@linux.intel.com, torvalds@linux-foundation.org,
        gregkh@linux-foundation.org
User-Agent: SquirrelMail/1.4.22-21.fc27
MIME-Version: 1.0
Content-Type: text/plain;charset=utf-8
Content-Transfer-Encoding: 8bit
Importance: Normal
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


> On 01/21/2018, 10:49 AM, David Woodhouse wrote:
>> Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and
>> ARCH_CAPABILITIES.
>>
>> See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf
>>
>> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
>> ---
>>  arch/x86/include/asm/msr-index.h | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h
>> b/arch/x86/include/asm/msr-index.h
>> index fa11fb1..3e50463 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -42,6 +42,13 @@
>>  #define MSR_PPIN_CTL			0x0000004e
>>  #define MSR_PPIN			0x0000004f
>>
>> +#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
>> +#define SPEC_CTRL_IBRS			(1 << 0)   /* Indirect Branch Restricted
>> Speculation */
>> +#define SPEC_CTRL_STIBP			(1 << 1)   /* Single Thread Indirect Branch
>> Predictors */
>> +
>> +#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
>> +#define PRED_CMD_IBPB			(1 << 0)   /* Indirect Branch Prediction
>> Barrier */
>> +
>>  #define MSR_IA32_PERFCTR0		0x000000c1
>>  #define MSR_IA32_PERFCTR1		0x000000c2
>>  #define MSR_FSB_FREQ			0x000000cd
>> @@ -60,6 +67,10 @@
>>  #define MSR_IA32_BBL_CR_CTL		0x00000119
>>  #define MSR_IA32_BBL_CR_CTL3		0x0000011e
>>
>> +#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
>> +#define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
>> +#define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */
>
> Is there any reason why all 3 are not properly sorted?
> 0x04e > 0x048
> 0x119 > 0x10a

Er... no good reason. I was definitely *trying* to put them in the right
place. I plead incompetence; will fix...

-- 
dwmw2