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[209.132.180.67]) by mx.google.com with ESMTP id a11-v6si3512136plt.567.2018.01.22.05.29.46; Mon, 22 Jan 2018 05:30:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=AU17uEWa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751191AbeAVN3X (ORCPT + 99 others); Mon, 22 Jan 2018 08:29:23 -0500 Received: from mail-ot0-f177.google.com ([74.125.82.177]:37914 "EHLO mail-ot0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751086AbeAVN3T (ORCPT ); Mon, 22 Jan 2018 08:29:19 -0500 Received: by mail-ot0-f177.google.com with SMTP id v5so7426024oth.5 for ; Mon, 22 Jan 2018 05:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=lrPmfOCggsTSB3e4q9nQ8inuck23f3L6FQjL5vmq2o0=; b=AU17uEWaJKctJdJUky+kDzEet81E7DUOU0iYSuP+oVsTpC+c6xRlaY9QqshPyAnH37 IphHIphc6Fr3++DnH6YGW+jqpvp41EFq4vatFYu9NcSybJe6t0yMWEjXMsQvEPAgovVu CzMA92jjpRFRhqxwA+8A+f4kwACr6g0HkX0dI7f3JuwL5RnOlgw0GaJ5MpcMKfzgGIm5 oveQYWzGR6y5dPdgnkvi9DPt9wtG0VSxKBTzkBWV/XQ5CSP3gCermiBRcYIotOeWjkwT kOjVq1SpXYR9HCGNqLIgdlTgmDPNi0R8PoVFVXMCQ9otPom3qe1hHNsm9bHaT/4G/2Uu 6CMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lrPmfOCggsTSB3e4q9nQ8inuck23f3L6FQjL5vmq2o0=; b=TDoqZlVJyOQR0+Qq8bs0DkykvnvCYZVGc5lELw5iZHRrMTeZta4VF49gNasZXAOSXC jR6fDcGfzqy4lLCRu+X02jfpx/YSY1i16LIRVJmirnbYcL3rqIXcAgKIor2ypXPAHkIT EqTNvpqBNxa7gezKsx2+MtRCapm3m/0CebkBep8+ZWbP/DPI0Z1fm2YcXO0uv9SUCKcQ au9zblViZ5VjVzS+9GYzlOhvWRV0SZqebkfgNgxIG1tKdGETInwFTgYAZYA422qg8FIH 7SYceD7gVKZ1LvL7uIQjkqeQLd008d4Wbf80Hj2eDlPHlbija0zBFxEAR9f45EZNvEcE FwVA== X-Gm-Message-State: AKwxytcQzjMns+FjjadX1ZP3RKNEpT6nwAKvm0WaCgNgsLa2GSW3EI4g v9DEMms7g4pKYDBDyY3dR5e5SNfoXjtBI5sgyE4dKA== X-Received: by 10.157.54.226 with SMTP id s31mr4016683otd.280.1516627758418; Mon, 22 Jan 2018 05:29:18 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.24.23 with HTTP; Mon, 22 Jan 2018 05:29:17 -0800 (PST) In-Reply-To: <1516468460-4908-1-git-send-email-david@lechnology.com> References: <1516468460-4908-1-git-send-email-david@lechnology.com> From: Bartosz Golaszewski Date: Mon, 22 Jan 2018 14:29:17 +0100 Message-ID: Subject: =?UTF-8?Q?Re=3A_=5BPATCH_v6_00=2F41=5D_ARM=3A_davinci=3A_convert_to_common?= =?UTF-8?Q?_clock_framework=E2=80=8B?= To: David Lechner Cc: linux-clk@vger.kernel.org, devicetree , linux-arm-kernel@lists.infradead.org, Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-01-20 18:13 GMT+01:00 David Lechner : > This series converts mach-davinci to use the common clock framework. > > The series works like this, the first 19 patches create new clock drivers > using the common clock framework. There are basically 3 groups of clocks - > PLL, PSC and CFGCHIP (syscon). There are six different SoCs that each have > unique init data, which is the reason for so many patches. > > Then, starting with "ARM: da830: add new clock init using common clock", > we get the mach code ready for the switch by adding the code needed for > the new clock drivers and adding #ifndef CONFIG_COMMON_CLK around the > legacy clocks so that we can switch easily between the old and the new. > > "ARM: davinci: switch to common clock framework" actually flips the switch > to start using the new clock drivers. Then the next 8 patches remove all > of the old clock code. > > The final three patches add device tree clock support to the one SoC that > supports it. > > v6 changes (also see individual patches for details): > - All of the device tree bindings are changed > - All of the clock drivers are changed significantly > - Fixed issues brought up during review of v5 > - "ARM: davinci: move davinci_clk_init() to init_time" is removed from this > series and submitted separately > > v5 changes: > - Basically, this is an entirely new series > - Patches are broken up into bite-sized pieces > - Converted PSC clock driver to use regmap > - Restored "force" flag for certain DA850 clocks > - Added device tree bindings > - Moved more of the clock init to drivers/clk > - Fixed frequency scaling (maybe*) > > * I have frequency scaling using cpufreq-dt, so I know the clocks are doing > what they need to do to make this work, but I haven't figured out how to > test davinci-cpufreq driver yet. (Patches to make cpufreq-dt work will be > sent separately after this series has landed.) > This driver doesn't have DT support - I suppose it would be useful to add it and also add the corresponding DT node to da850.dtsi. If you're ok with it, I can start working on it. I also have a patch for the i2c cpufreq issue and it would be nice to test it with it. Thanks, Bartosz