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[209.132.180.67]) by mx.google.com with ESMTP id w18si12973144iof.235.2018.01.22.07.39.10; Mon, 22 Jan 2018 07:39:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751121AbeAVPir (ORCPT + 99 others); Mon, 22 Jan 2018 10:38:47 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:5145 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750828AbeAVPip (ORCPT ); Mon, 22 Jan 2018 10:38:45 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w0MFYI9x026825; Mon, 22 Jan 2018 16:38:16 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fnaj6jhnp-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 22 Jan 2018 16:38:16 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4183134; Mon, 22 Jan 2018 15:38:16 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1C0462C85; Mon, 22 Jan 2018 15:38:16 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.352.0; Mon, 22 Jan 2018 16:38:16 +0100 Received: from localhost (10.201.23.32) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Mon, 22 Jan 2018 16:38:15 +0100 From: Philippe Cornu To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , David Airlie , "Rob Herring" , Mark Rutland , "Maxime Coquelin" , Alexandre Torgue , , , , CC: Mickael Reulier , Gabriel Fernandez , Ludovic Barre Subject: [PATCH] dt-bindings: display: stm32: add pixel clock mandatory property Date: Mon, 22 Jan 2018 16:38:05 +0100 Message-ID: <20180122153805.23720-1-philippe.cornu@st.com> X-Mailer: git-send-email 2.15.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-22_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the DPI/RGB input pixel clock in mandatory properties because it really offers a better preciseness for timing computations. Signed-off-by: Philippe Cornu --- Please apply "dt-bindings: display: stm32: correct clock-names in dsi panel example" before this patch. Changes in v3: remove the note regarding swapped clock names (now in a separate patch). Changes in v2: put new clock in last position (Rob Herring) Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 3eb1b48b47dd..942b7237ae87 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -29,6 +29,7 @@ Mandatory properties specific to STM32 DSI: - compatible: "st,stm32-dsi". - clock-names: - phy pll reference clock string name, must be "ref". + - DPI/RGB input pixel clock string name, must be "px_clk". - resets: see [5]. - reset-names: see [5]. @@ -97,8 +98,9 @@ Example 2: DSI panel #size-cells = <0>; compatible = "st,stm32-dsi"; reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>, + <&rcc 1 CLK_LCD>; + clock-names = "pclk", "ref", "px_clk"; resets = <&rcc STM32F4_APB2_RESET(DSI)>; reset-names = "apb"; -- 2.15.1