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[209.132.180.67]) by mx.google.com with ESMTP id l42si12822284ioi.324.2018.01.22.08.03.17; Mon, 22 Jan 2018 08:03:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=OP8alb6e; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751331AbeAVQBU (ORCPT + 99 others); Mon, 22 Jan 2018 11:01:20 -0500 Received: from mail-ua0-f193.google.com ([209.85.217.193]:32799 "EHLO mail-ua0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751028AbeAVQBP (ORCPT ); Mon, 22 Jan 2018 11:01:15 -0500 Received: by mail-ua0-f193.google.com with SMTP id p12so3561000uad.0; Mon, 22 Jan 2018 08:01:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=k1hQG/Y901u6PX3V0PHU2Tt0ssaatWps5pLIekHIXJA=; b=OP8alb6eyy6eXDaR6rUgk6oNBdbsfnigiSte/+IaZvOL2ak88cK7lzLAUezr1RA9F5 +TFMB2nvDPV/VUHNEnJt01yC9lGYGZcu2oMjytCPa2BIZxmXxOJd3iEpL+sURhsDaYkN E+Uvzu4adq0YiH9zL8jLFAwXK5MGX0jGYHp6i8lEjL8Fl5P/beo3hsu7ItIHAMoS7Een qU05MXvAUNgPomKE2k9WFdJey+HkwMQ95X4CyfJz3iAjLrbW9X27oa7GGa91tPnaRqVf s3t9piIboLJnpQuIAN3l5BPqs6F9NtCxqkgASVfvmv17KQxRfR+5xlrJlQCKc5hukjjq doVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=k1hQG/Y901u6PX3V0PHU2Tt0ssaatWps5pLIekHIXJA=; b=nHqO5FmwF4r+r2Y9UpEjU0k2EhM5AjTsw8DLSlCRq7270vNMbAOrQJsc0qXfOGEmyn gXpJiBob3MJOwfp6KOfZuT7hhnu1Od/fN++LG/vo2DHzI4iQ3kSjzJjqCQXRuVm7Y5+M KW9iaSqAdspUfCl/sDedA5nf/UVDg8DEzWaLE4wz/WLEieTsJ/41tEsHQvIFYCtdiOZN pwO3Mk+vgU2BCvc+8XMQEOV1Yj8X9em+iM2rzZibyeWDexSSC88nyJ/h4JmQbHDRPc4Z gicXw43vZGphJJxhhIsL48U27IEz62jvqdT6rbAfsxu++hK69l+Lo8GnssYH0KbRCGpr O2mQ== X-Gm-Message-State: AKwxyteMjFU/VLpkLe5t7UIuCkk1SEkXOSWDRbF0v47FgY7We0VzozXI +a+uV0OUbtxVIq2Yd6nPgY0f1FIemnhU2MVYmmU= X-Received: by 10.159.46.18 with SMTP id t18mr5207223uaj.91.1516636874590; Mon, 22 Jan 2018 08:01:14 -0800 (PST) MIME-Version: 1.0 Received: by 10.159.42.194 with HTTP; Mon, 22 Jan 2018 08:00:34 -0800 (PST) In-Reply-To: References: From: Greentime Hu Date: Tue, 23 Jan 2018 00:00:34 +0800 Message-ID: Subject: Re: [PATCH v6 29/36] nds32: Build infrastructure To: Arnd Bergmann Cc: Greentime , Linux Kernel Mailing List , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Networking , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial@vger.kernel.org, Geert Uytterhoeven , Linus Walleij , Mark Rutland , Greg KH , Guo Ren , Randy Dunlap , David Miller , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Vincent Chen Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Arnd: 2018-01-22 23:38 GMT+08:00 Arnd Bergmann : > On Mon, Jan 22, 2018 at 4:20 PM, Greentime Hu wrote: > BE >>> >>> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver >>> should rely on that. >> >> I will drop it. >> >>>> +choice >>>> + prompt "CPU type" >>>> + default CPU_V3 >>>> +config CPU_N15 >>>> + bool "AndesCore N15" >>>> +config CPU_N13 >>>> + bool "AndesCore N13" >>>> + select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB >>>> +config CPU_N10 >>>> + bool "AndesCore N10" >>>> + select CPU_CACHE_ALIASING >>>> +config CPU_D15 >>>> + bool "AndesCore D15" >>>> +config CPU_D10 >>>> + bool "AndesCore D10" >>>> + select CPU_CACHE_ALIASING >>>> +config CPU_V3 >>>> + bool "AndesCore v3 compatible" >>>> + select ANDES_PAGE_SIZE_8KB >>>> +endchoice >>> >>> I forget what we discussed here earlier, but at the very least, there should be >>> some help text here to explain what the implications are. I assume that you >>> generally want to be able to build one kernel to run on all of the above, right? >>> >>> Will selecting 'CPU_V3' result in a kernel binary that can run on all of them? >>> If so, please explain it here as that is not obvious. >>> >>> For the other CPU types, can you list the what backwards-compatiblity >>> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10? >>> >> Yes, we would like to build a kernel with CPU_V3 to run on all of the above. >> >> Not sure if these help texts clear enough? >> >> choice >> prompt "CPU type" >> default CPU_V3 >> help >> The data cache of N15/D15 is implemented as PIPT and it will >> not cause the >> cache aliasing issue. The rest cpus(N13, N10 and D10) are >> implemented as >> VIPT data cache. It may cause the cache aliasing issue if >> its cache way >> size is larger than page size. You can specify the the CPU >> type direcly or >> choose CPU_V3 if unsure. >> >> A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. >> A kernel built for N15 is able to run on N15 or D15. >> A kernel built for D10 is able to run on D10 or D15. >> A kernel built for D15 is able to run on D15. >> A kernel built for N13 with CPU_CACHE_ALIASING is able to >> run on N15, D15, N13, N10 or D10 >> A kernel built for N13 without CPU_CACHE_ALIASING is able to >> run on N15, N13 or D15 >> >> config CPU_N15 >> bool "AndesCore N15" >> config CPU_N13 >> bool "AndesCore N13" >> select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB >> config CPU_N10 >> bool "AndesCore N10" >> select CPU_CACHE_ALIASING >> config CPU_D15 >> bool "AndesCore D15" >> config CPU_D10 >> bool "AndesCore D10" >> select CPU_CACHE_ALIASING >> config CPU_V3 >> bool "AndesCore v3 compatible" >> select CPU_CACHE_ALIASING >> endchoice > > I would drop the description about CPU_CACHE_ALIASING in the list > of compatibilities text and simply say 'A kernel built for N13 is able to run > on N15, N13 or D15', it's more logical that way, and it gives you the freedom > to later change the rules about whether it can or cannot run. > > Maybe also change the initial prompt from "CPU type" to "minimum CPU type". > Thank you for your suggestion. I will update it like this. choice prompt "minimum CPU type" default CPU_V3 help The data cache of N15/D15 is implemented as PIPT and it will not cause the cache aliasing issue. The rest cpus(N13, N10 and D10) are implemented as VIPT data cache. It may cause the cache aliasing issue if its cache way size is larger than page size. You can specify the CPU type direcly or choose CPU_V3 if unsure. A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. A kernel built for N15 is able to run on N15 or D15. A kernel built for D10 is able to run on D10 or D15. A kernel built for D15 is able to run on D15. A kernel built for N13 is able to run on N15, N13 or D15. config CPU_N15 bool "AndesCore N15" config CPU_N13 bool "AndesCore N13" select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB config CPU_N10 bool "AndesCore N10" select CPU_CACHE_ALIASING config CPU_D15 bool "AndesCore D15" config CPU_D10 bool "AndesCore D10" select CPU_CACHE_ALIASING config CPU_V3 bool "AndesCore v3 compatible" select CPU_CACHE_ALIASING endchoice