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[209.132.180.67]) by mx.google.com with ESMTP id g33si13324406iod.118.2018.01.22.10.14.13; Mon, 22 Jan 2018 10:14:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751259AbeAVSNJ (ORCPT + 99 others); Mon, 22 Jan 2018 13:13:09 -0500 Received: from mail.kernel.org ([198.145.29.99]:49604 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751117AbeAVSNG (ORCPT ); Mon, 22 Jan 2018 13:13:06 -0500 Received: from mail-qt0-f170.google.com (mail-qt0-f170.google.com [209.85.216.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3071621787; Mon, 22 Jan 2018 18:13:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3071621787 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=robh@kernel.org Received: by mail-qt0-f170.google.com with SMTP id g14so13938113qti.2; Mon, 22 Jan 2018 10:13:06 -0800 (PST) X-Gm-Message-State: AKwxytfw5FiQkQGySVabyd865yGs5VdH2MHoKGX7BYad+tzVnCGWIY2y sUrWKAMQH3kEn/h9Zd37T1ue1zHsmzAr/xpPaQ== X-Received: by 10.237.58.226 with SMTP id o89mr12142000qte.207.1516644785367; Mon, 22 Jan 2018 10:13:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.147.20 with HTTP; Mon, 22 Jan 2018 10:12:44 -0800 (PST) In-Reply-To: References: <1515766983-15151-1-git-send-email-claudiu.beznea@microchip.com> <1515766983-15151-11-git-send-email-claudiu.beznea@microchip.com> <20180119223452.doeqfd4aewkf5fla@rob-hp-laptop> From: Rob Herring Date: Mon, 22 Jan 2018 12:12:44 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 10/16] pwm: Add PWM modes To: Claudiu Beznea Cc: Thierry Reding , Mark Rutland , Russell King , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jonathan Corbet , Nicolas Ferre , Alexandre Belloni , Linux PWM List , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-amlogic@lists.infradead.org, "open list:ARM/Rockchip SoC..." , "moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 22, 2018 at 2:54 AM, Claudiu Beznea wrote: > > > On 20.01.2018 00:34, Rob Herring wrote: >> On Fri, Jan 12, 2018 at 04:22:57PM +0200, Claudiu Beznea wrote: >>> Define a macros for PWM modes to be used by device tree sources. >>> >>> Signed-off-by: Claudiu Beznea >>> --- >>> include/dt-bindings/pwm/pwm.h | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h >>> index ab9a077e3c7d..b8617431f8ec 100644 >>> --- a/include/dt-bindings/pwm/pwm.h >>> +++ b/include/dt-bindings/pwm/pwm.h >>> @@ -12,4 +12,7 @@ >>> >>> #define PWM_POLARITY_INVERTED (1 << 0) >>> >>> +#define PWM_DTMODE_NORMAL (1 << 0) >> >> Bit 0 is already taken. I think you mean (0 << 1)? > I wanted to have the PWM modes in a new cell, so that the pwms binding to be > something like: > pwms= > > If you think it is mode feasible to also include PWM mode in the cell for > PWM flags, please let me know. Yes, but you have to make "normal" be no bit set to be compatible with everything already out there. >> Personally, I'd just drop this define. A define for a 0 value makes more >> sense when each state is equally used (like active high or low), but if >> 0 is the more common case, then I don't the need for a define. > I want it to have these defines like bit defines: > PWM_DTMODE_NORMAL=0x1 > PWM_DTMODE_COMPLEMENTARY=0x2 > PWM_DTMODE_PUSH_PULL=0x4 Thinking about this some more, shouldn't the new modes just be implied? A client is going to require one of these modes or it won't work right. Also complementary mode could be accomplished with a single pwm output and a board level inverter, right? How would that be handled when the PWM driver doesn't support that mode? Rob