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[209.132.180.67]) by mx.google.com with ESMTP id c41-v6si2910881plj.682.2018.01.23.01.51.18; Tue, 23 Jan 2018 01:51:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751243AbeAWJuz (ORCPT + 99 others); Tue, 23 Jan 2018 04:50:55 -0500 Received: from foss.arm.com ([217.140.101.70]:38906 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751187AbeAWJuy (ORCPT ); Tue, 23 Jan 2018 04:50:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C158080D; Tue, 23 Jan 2018 01:50:53 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 922FF3F41F; Tue, 23 Jan 2018 01:50:53 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id D48C71AE2FFF; Tue, 23 Jan 2018 09:51:01 +0000 (GMT) Date: Tue, 23 Jan 2018 09:51:01 +0000 From: Will Deacon To: Jon Masters Cc: Jayachandran C , marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org Subject: Re: [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2 Message-ID: <20180123095101.GA1686@arm.com> References: <20180118135354.GB20783@arm.com> <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> <20180122113311.GB15456@arm.com> <2232c6e4-c55f-4e57-c58f-2bfc02b2fac2@jonmasters.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2232c6e4-c55f-4e57-c58f-2bfc02b2fac2@jonmasters.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 22, 2018 at 02:00:59PM -0500, Jon Masters wrote: > On 01/22/2018 06:33 AM, Will Deacon wrote: > > On Fri, Jan 19, 2018 at 04:22:47AM -0800, Jayachandran C wrote: > >> Use PSCI based mitigation for speculative execution attacks targeting > >> the branch predictor. We use the same mechanism as the one used for > >> Cortex-A CPUs, we expect the PSCI version call to have a side effect > >> of clearing the BTBs. > >> > >> Signed-off-by: Jayachandran C > >> --- > >> arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ > >> 1 file changed, 10 insertions(+) > >> > >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > >> index 70e5f18..45ff9a2 100644 > >> --- a/arch/arm64/kernel/cpu_errata.c > >> +++ b/arch/arm64/kernel/cpu_errata.c > >> @@ -338,6 +338,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > >> .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, > >> MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), > >> }, > >> + { > >> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, > >> + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), > >> + .enable = enable_psci_bp_hardening, > >> + }, > >> + { > >> + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, > >> + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), > >> + .enable = enable_psci_bp_hardening, > >> + }, > >> #endif > > > > Thanks. > > > > Acked-by: Will Deacon > > Thanks. I have separately asked for a specification tweak to allow us to > discover whether firmware has been augmented to provide the necessary > support that we need. That applies beyond Cavium. AFAIK, there's already an SMCCC/PSCI proposal doing the rounds that is discoverable and does what we need. Have you seen it? We should be posting code this week. Will