Received: by 10.223.176.46 with SMTP id f43csp4003377wra; Tue, 23 Jan 2018 02:41:06 -0800 (PST) X-Google-Smtp-Source: AH8x227Zr+QMYr2ozAvREXqK9p5NTRTxNTRw4UnUlGk0065H07HQ0Ke8VF9+6E80DlBXfR3sqMcH X-Received: by 10.98.153.2 with SMTP id d2mr10313664pfe.44.1516704066618; Tue, 23 Jan 2018 02:41:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516704066; cv=none; d=google.com; s=arc-20160816; b=d8+O39PMDBzTzCkUC+TZEn/cvX6ZWAlHNcIrXV0o4DuAjD/ax815XYYiIqi3zlJAQ9 l15++Khf9ijaNaYmWaT0gYA2UrAsj77Ev7brhdcZCQi6yQuAKyy+PE6vRtRPt5zqHf/Q /zAREEr7G3m98QJKgjM++77HuQeaPTMV4ISmizpEOBfXvzPvAhWA/1bamj3YT+HZLBGU 6NifXBHR2BKflmsSsOSig8ZmDMzdmKwEcu6G86PBWdUDgTFqQ91GqQW9c1S3HUslDc84 LEAPBNLuT1M4MutME4MC7oMXypgd9EzVz/ATeWKDqJ6VeyUQZVrv3rHdlHB3mcbXf+K+ ZiLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:arc-authentication-results; bh=VuDCt6LzMd/Zi5LcOsUnXahmDnBePvwOTcAMCpRHbRs=; b=LgQOtRgClkfTEkZj9F9u9pvvXV6m381/DxeqyIxjs3wxSDEhgJNeJ6L3OryrYjj/ua t0ztzca5RDtdb1sVHwfb0cVHxQMA6jMm2VDeW+rkgolh6NA9qbzhaSWUOWmO5lg9IJw3 o9sJ3Pu9abujdYN3e3wLv9dvmtGMWxLOAF+H5v/TEACsOHZ9laWBXI6hgXwhbFpZioDc +oDJZQO2eZ/z9WMT0+qkeKQQWqhegDoRSZROqUFkDmk0sHcxFGE89lbOdlnEqNTa3fkp B0hfbuMwiy/8LNWhdKQ75RFJsupMfxbcQVFbpl9uUr27HJYARHI0ErvbmNwYpGIkXvc5 P1XA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o12-v6si4528496plk.60.2018.01.23.02.40.50; Tue, 23 Jan 2018 02:41:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751408AbeAWKk1 (ORCPT + 99 others); Tue, 23 Jan 2018 05:40:27 -0500 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:45749 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751154AbeAWKk0 (ORCPT ); Tue, 23 Jan 2018 05:40:26 -0500 X-IronPort-AV: E=Sophos;i="5.46,400,1511852400"; d="scan'208";a="10784779" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 23 Jan 2018 03:40:25 -0700 Received: from [10.145.6.87] (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.352.0; Tue, 23 Jan 2018 03:40:24 -0700 Subject: Re: [PATCH v2 10/16] pwm: Add PWM modes To: Rob Herring CC: Thierry Reding , Mark Rutland , Russell King , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jonathan Corbet , Nicolas Ferre , Alexandre Belloni , Linux PWM List , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , , "open list:ARM/Rockchip SoC..." , "moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1515766983-15151-1-git-send-email-claudiu.beznea@microchip.com> <1515766983-15151-11-git-send-email-claudiu.beznea@microchip.com> <20180119223452.doeqfd4aewkf5fla@rob-hp-laptop> From: Claudiu Beznea Message-ID: <759435bf-764f-68ea-de51-c878ceec28e2@microchip.com> Date: Tue, 23 Jan 2018 12:40:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22.01.2018 20:12, Rob Herring wrote: > On Mon, Jan 22, 2018 at 2:54 AM, Claudiu Beznea > wrote: >> >> >> On 20.01.2018 00:34, Rob Herring wrote: >>> On Fri, Jan 12, 2018 at 04:22:57PM +0200, Claudiu Beznea wrote: >>>> Define a macros for PWM modes to be used by device tree sources. >>>> >>>> Signed-off-by: Claudiu Beznea >>>> --- >>>> include/dt-bindings/pwm/pwm.h | 3 +++ >>>> 1 file changed, 3 insertions(+) >>>> >>>> diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h >>>> index ab9a077e3c7d..b8617431f8ec 100644 >>>> --- a/include/dt-bindings/pwm/pwm.h >>>> +++ b/include/dt-bindings/pwm/pwm.h >>>> @@ -12,4 +12,7 @@ >>>> >>>> #define PWM_POLARITY_INVERTED (1 << 0) >>>> >>>> +#define PWM_DTMODE_NORMAL (1 << 0) >>> >>> Bit 0 is already taken. I think you mean (0 << 1)? >> I wanted to have the PWM modes in a new cell, so that the pwms binding to be >> something like: >> pwms= >> >> If you think it is mode feasible to also include PWM mode in the cell for >> PWM flags, please let me know. > > Yes, but you have to make "normal" be no bit set to be compatible with > everything already out there. I'm thinking having it separately is more clear and modular. > >>> Personally, I'd just drop this define. A define for a 0 value makes more >>> sense when each state is equally used (like active high or low), but if >>> 0 is the more common case, then I don't the need for a define. >> I want it to have these defines like bit defines: >> PWM_DTMODE_NORMAL=0x1 >> PWM_DTMODE_COMPLEMENTARY=0x2 >> PWM_DTMODE_PUSH_PULL=0x4 > > Thinking about this some more, shouldn't the new modes just be > implied? A client is going to require one of these modes or it won't > work right. The clients could or could not request the mode via DT. Every PWM chip registers supported modes at driver probe (default, if no PWM mode support is added to the PWM chip driver the PWM chip will supports only normal mode). If a PWM channel is requested by a PWM client via DT, and there is no PWM mode setting in DT bindings, e.g. requested with these bindings: pwms= or pwms= the first available mode of PWM chip will be used to instantiate the mode. If the defined modes are: PWM_DTMODE_NORMAL=0x1 PWM_DTMODE_COMPLEMENTARY=0x2 PWM_DTMODE_PUSH_PULL=0x4 and the PWM chip driver registers itself, at probe, with (PWM_DTMODE_COMPLEMENTARY | PWM_DTMODE_PUSH_PULL) then the first available mode will be PWM_DTMODE_COMPLEMENTARY (first LSB bit of the variable that keeps the available modes). > > Also complementary mode could be accomplished with a single pwm output > and a board level inverter, right? Yes, I think this could be accomplished. Here I took into account only PWM controller capabilities. Having this, I think will involve having extra PWM bindings describing extra capabilities per-channel. And to change a little bit the implementation in order to have these capabilities per channel nor per PWM controller. What do you think? I think push-pull mode could also be accomplished having board inverter and delay modules. So, in these cases make sense to have per channel capabilities, as per my understanding. Thank you, Claudiu Beznea How would that be handled when the > PWM driver doesn't support that mode? > > Rob >