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[209.132.180.67]) by mx.google.com with ESMTP id z66si8327681itg.26.2018.01.23.07.22.38; Tue, 23 Jan 2018 07:22:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751312AbeAWPVg (ORCPT + 99 others); Tue, 23 Jan 2018 10:21:36 -0500 Received: from mail.kernel.org ([198.145.29.99]:40090 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750911AbeAWPVe (ORCPT ); Tue, 23 Jan 2018 10:21:34 -0500 Received: from mail-qt0-f181.google.com (mail-qt0-f181.google.com [209.85.216.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7F31321795; Tue, 23 Jan 2018 15:21:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7F31321795 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=robh@kernel.org Received: by mail-qt0-f181.google.com with SMTP id z11so2164061qtm.3; Tue, 23 Jan 2018 07:21:33 -0800 (PST) X-Gm-Message-State: AKwxytcyvooI47ztlG1apqY86CjWFHcDD2prp8cn4bUqMrS9ji1TM/+C fQtZEkM0jxa+Guw2BEpV2XrhUTOeGUtnVA4/Hw== X-Received: by 10.200.9.82 with SMTP id z18mr4070432qth.87.1516720892622; Tue, 23 Jan 2018 07:21:32 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.147.20 with HTTP; Tue, 23 Jan 2018 07:21:12 -0800 (PST) In-Reply-To: <759435bf-764f-68ea-de51-c878ceec28e2@microchip.com> References: <1515766983-15151-1-git-send-email-claudiu.beznea@microchip.com> <1515766983-15151-11-git-send-email-claudiu.beznea@microchip.com> <20180119223452.doeqfd4aewkf5fla@rob-hp-laptop> <759435bf-764f-68ea-de51-c878ceec28e2@microchip.com> From: Rob Herring Date: Tue, 23 Jan 2018 09:21:12 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 10/16] pwm: Add PWM modes To: Claudiu Beznea Cc: Thierry Reding , Mark Rutland , Russell King , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jonathan Corbet , Nicolas Ferre , Alexandre Belloni , Linux PWM List , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-amlogic@lists.infradead.org, "open list:ARM/Rockchip SoC..." , "moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 23, 2018 at 4:40 AM, Claudiu Beznea wrote: > > > On 22.01.2018 20:12, Rob Herring wrote: >> On Mon, Jan 22, 2018 at 2:54 AM, Claudiu Beznea >> wrote: >>> >>> >>> On 20.01.2018 00:34, Rob Herring wrote: >>>> On Fri, Jan 12, 2018 at 04:22:57PM +0200, Claudiu Beznea wrote: >>>>> Define a macros for PWM modes to be used by device tree sources. >>>>> >>>>> Signed-off-by: Claudiu Beznea >>>>> --- >>>>> include/dt-bindings/pwm/pwm.h | 3 +++ >>>>> 1 file changed, 3 insertions(+) >>>>> >>>>> diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h >>>>> index ab9a077e3c7d..b8617431f8ec 100644 >>>>> --- a/include/dt-bindings/pwm/pwm.h >>>>> +++ b/include/dt-bindings/pwm/pwm.h >>>>> @@ -12,4 +12,7 @@ >>>>> >>>>> #define PWM_POLARITY_INVERTED (1 << 0) >>>>> >>>>> +#define PWM_DTMODE_NORMAL (1 << 0) >>>> >>>> Bit 0 is already taken. I think you mean (0 << 1)? >>> I wanted to have the PWM modes in a new cell, so that the pwms binding to be >>> something like: >>> pwms= >>> >>> If you think it is mode feasible to also include PWM mode in the cell for >>> PWM flags, please let me know. >> >> Yes, but you have to make "normal" be no bit set to be compatible with >> everything already out there. > I'm thinking having it separately is more clear and modular. Having a standard number of cells (and fields in cells) is easier to maintain. We've set this at 3 for PWMs and you have already found what happens when you have a different number of cells. Adding a 4th cell (and possibly a different form of 3 cells in the case of no channel # cell) just creates more combinations to parse. And we don't want to go update all the existing users using 3 cells to use 4 cells just to align. If the mode needed to be set in the common case, then I might feel differently about having a separate cell. But these modes seem like a special case. How many PWM controllers actually support modes like these? >>>> Personally, I'd just drop this define. A define for a 0 value makes more >>>> sense when each state is equally used (like active high or low), but if >>>> 0 is the more common case, then I don't the need for a define. >>> I want it to have these defines like bit defines: >>> PWM_DTMODE_NORMAL=0x1 >>> PWM_DTMODE_COMPLEMENTARY=0x2 >>> PWM_DTMODE_PUSH_PULL=0x4 >> >> Thinking about this some more, shouldn't the new modes just be >> implied? A client is going to require one of these modes or it won't >> work right. > The clients could or could not request the mode via DT. Every PWM chip registers > supported modes at driver probe (default, if no PWM mode support is added > to the PWM chip driver the PWM chip will supports only normal mode). If a > PWM channel is requested by a PWM client via DT, and there is no PWM mode setting > in DT bindings, e.g. requested with these bindings: > pwms= or > pwms= > the first available mode of PWM chip will be used to instantiate the mode. > If the defined modes are: > PWM_DTMODE_NORMAL=0x1 > PWM_DTMODE_COMPLEMENTARY=0x2 > PWM_DTMODE_PUSH_PULL=0x4 > and the PWM chip driver registers itself, at probe, with (PWM_DTMODE_COMPLEMENTARY | PWM_DTMODE_PUSH_PULL) > then the first available mode will be PWM_DTMODE_COMPLEMENTARY (first LSB bit > of the variable that keeps the available modes). Every driver already supports "normal", so that's implied. It would be pointless to make every driver register that explicitly. It would be pretty hard to not support normal as that's just ignore the 2nd signal. >> Also complementary mode could be accomplished with a single pwm output >> and a board level inverter, right? > Yes, I think this could be accomplished. Here I took into account only PWM controller > capabilities. Having this, I think will involve having extra PWM bindings describing > extra capabilities per-channel. And to change a little bit the implementation in order > to have these capabilities per channel nor per PWM controller. What do you think? > > I think push-pull mode could also be accomplished having board inverter and delay > modules. So, in these cases make sense to have per channel capabilities, as per my > understanding. Yes, it certainly is per channel. You may or may not have the 2nd pin on any given channel. But again, if the client needs one of these modes, then the h/w must be hooked up correctly to a channel with 2 signals. Rob