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To: "Manfred Spraul" <manfred@colorfullife.com>
Cc: "Mark Hemment" <markhe@veritas.com>, <linux-kernel@vger.kernel.org>
Subject: Re: Q: explicit alignment control for the slab allocator
In-Reply-To: <Pine.LNX.4.21.0103011800460.11260-100000@alloc> <3A9EA940.CB82665C@colorfullife.com> <d3lmqhny9w.fsf@lxplus015.cern.ch> <003601c0a746$57ab5750$5517fea9@local>
From: Jes Sorensen <jes@linuxcare.com>
Date: 08 Mar 2001 18:30:12 +0100
In-Reply-To: "Manfred Spraul"'s message of "Wed, 7 Mar 2001 21:32:45 +0100"
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>>>>> "Manfred" == Manfred Spraul <manfred@colorfullife.com> writes:

Manfred> First of all HW_CACHEALIGN aligns to the L1 cache, not
Manfred> SMP_CACHE_BYTES.  Additionally you sometimes need a
Manfred> guaranteed alignment for other problems, afaik ARM needs 1024
Manfred> bytes for some structures due to cpu restrictions, and
Manfred> several usb controllers need 16 byte alignment.

My question is whats the point in asking for L1_CACHE_BYTES alignment
for hardware reasons when you can't see it beyond the cache controller
anyway? Sure it makes sense for data structures only used by the CPU,
but for structures that are shared between CPUs or goes to DMA
controllers it seems to make little sense.

Jes
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