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[209.132.180.67]) by mx.google.com with ESMTP id x4si8626211itg.87.2018.01.23.08.42.28; Tue, 23 Jan 2018 08:42:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AfQEQlvR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751983AbeAWQlj (ORCPT + 99 others); Tue, 23 Jan 2018 11:41:39 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46801 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751916AbeAWQlZ (ORCPT ); Tue, 23 Jan 2018 11:41:25 -0500 Received: by mail-wm0-f68.google.com with SMTP id 143so3054116wma.5 for ; Tue, 23 Jan 2018 08:41:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=sAbc7RiKIRai5zhiwM6dN89Oo3o/SEnFqiOjnxxzdkg=; b=AfQEQlvRuOohbqw3hLCIe3sUbpSE7GAqUNkYmDrodwxBzpPyFz7d1RlO46x1+Uwy5t EEyDTuMha5R63epQlanj04DApGErKP9p25D/bRbef8gKTlTPVJLEn6IrrwV22pTtl2ZW RNFbfRM+8K5jmpFD8xD9XJXxvJPpxfPRKSyLo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=sAbc7RiKIRai5zhiwM6dN89Oo3o/SEnFqiOjnxxzdkg=; b=TTdnlggvXGwJfmOSoVbg7J39f5KqvQZB6SFpDvA9Rkxs/baG73fH7RnGtWyucpH4io kIWq97rjqzKEDT39W3fVEHVYTpx41LjUBaOxvbYlbjuvHAgUSHO10A9AMIIBQZHZ3a5P lX04eVjTkEGGo5/MyyjQT/gK8KsvHCWup4Yr/fHQ4pbDCXCtpXULV9S1CQME3Hor6U2u PIAVJ/rxtnDPk+qR8pef3OJIZsUc3YdSb5YDQ4FrJvNGYW9npFpB7c/AWo+gs3la0BBj rokfr7keNWK/bGSY7CHDtK8EBbRZ+HpsCtcAq7itmJ6WIMXPPDE1uenLKuNEmf79GvTN JydQ== X-Gm-Message-State: AKwxytf541ZskWBYtb70ofmH3oI+DtISRWpt7ub3dbBurwtc3+0GT8qS EvjBapa/vOrTNXtwme5A45F6MA== X-Received: by 10.28.236.157 with SMTP id h29mr2660891wmi.160.1516725684142; Tue, 23 Jan 2018 08:41:24 -0800 (PST) Received: from dell ([2.27.167.60]) by smtp.gmail.com with ESMTPSA id b48sm1009637wrd.69.2018.01.23.08.41.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2018 08:41:23 -0800 (PST) Date: Tue, 23 Jan 2018 16:41:21 +0000 From: Lee Jones To: Fabrice Gasnier Cc: thierry.reding@gmail.com, robh+dt@kernel.org, alexandre.torgue@st.com, benjamin.gaignard@linaro.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, benjamin.gaignard@st.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org Subject: Re: [PATCH 4/8] mfd: stm32-timers: add support for dmas Message-ID: <20180123164121.xjzhypqe2u5c7zza@dell> References: <1516106631-18722-1-git-send-email-fabrice.gasnier@st.com> <1516106631-18722-5-git-send-email-fabrice.gasnier@st.com> <20180123133234.xmep76cgdremnj47@dell> <20180123153035.2rvhspe2m5ej57op@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 23 Jan 2018, Fabrice Gasnier wrote: > On 01/23/2018 04:30 PM, Lee Jones wrote: > > On Tue, 23 Jan 2018, Fabrice Gasnier wrote: > > > >> On 01/23/2018 02:32 PM, Lee Jones wrote: > >>> On Tue, 16 Jan 2018, Fabrice Gasnier wrote: > >>> > >>>> STM32 Timers can support up to 7 dma requests: > >>>> 4 channels, update, compare and trigger. > >>>> Optionally request part, or all dmas from stm32-timers MFD core. > >>>> Also, keep reference of device's bus address to allow child drivers to > >>>> transfer data from/to device by using dma. > >>>> > >>>> Signed-off-by: Fabrice Gasnier > >>>> --- > >>>> drivers/mfd/stm32-timers.c | 37 ++++++++++++++++++++++++++++++++++++- > >>>> include/linux/mfd/stm32-timers.h | 14 ++++++++++++++ > >>>> 2 files changed, 50 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c > >>>> static int stm32_timers_probe(struct platform_device *pdev) > >>>> { > >>>> struct device *dev = &pdev->dev; > >>>> @@ -44,6 +61,7 @@ static int stm32_timers_probe(struct platform_device *pdev) > >>>> mmio = devm_ioremap_resource(dev, res); > >>>> if (IS_ERR(mmio)) > >>>> return PTR_ERR(mmio); > >>>> + ddata->phys_base = res->start; > >>> > >>> What do you use this for? > >> > >> This is used in in child driver (pwm) for capture data transfer by dma. > > > > Might be worth being clear about that. > > > > Perhaps pass in 'dma_base' (phys_base + offset) instead? > > I guess you've had a look at [PATCH 5/8] pwm: stm32: add capture > support. Are you talking about passing phys_base + TIM_DMAR ? I have and I am. > If this is the case, I'd prefer to keep phys base only if you don't > mind, and handle TIM_DMAR offset in pwm driver. This way, all dma slave > config is kept locally at one place. > Or do you mean something else ? > > Maybe I can add a comment here about this ? > Something like: > /* phys_base to be used by child driver, e.g. DMA burst mode */ I haven't seen the memory map for this device, so it's not easy for me to comment, but passing in the physical address of the parent MFD into a child device doesn't quite sit right with me. At what level does TIM_DMAR sit? Is it a child (PWM) specific property, or is it described at parent (Timer) level? -- Lee Jones Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog