Received: by 10.223.176.46 with SMTP id f43csp4414685wra; Tue, 23 Jan 2018 09:06:47 -0800 (PST) X-Google-Smtp-Source: AH8x226Vddp3GDANbeFuZHVjyVQDY8nTww9CxpBSWJfzCChdoHJIJD+R4o2JBipoReWWAXSB1AQ4 X-Received: by 10.36.163.136 with SMTP id p130mr4466052ite.49.1516727207518; Tue, 23 Jan 2018 09:06:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516727207; cv=none; d=google.com; s=arc-20160816; b=ZOlNtYtHKLokUtoOvi7/mRgRUoTui6XKvy3FPU0EyzXXinygL7s9w91bVhLGxxtzfi tzlbjA2ITJWLS5P0bj9OASi2nqewW4/RnqoAqqp5LtbX1//cF277DA8lH6tgkGGX/lRm hDkwqhegaW2dCPUJx2VBXSlE4XJlF0iY/eZZ8Q8CaymT5DBrmuOX2Q6ijK0SHJa9RXGN z+brBYoypoJJtlQVfomLE5mQRJV+ty79SSqOw9PIAXP6oQKm2xqlFTYHZDYTMFDw+fEs jBTJfwCZw8CuuNpCDA2E8HcmQpL4Wq9DpmbSg6nCSgv883qDJkj+hZfGjex4vHPIlIvj o6Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :references:in-reply-to:mime-version:dkim-signature :arc-authentication-results; bh=XRKh2JuFYYP7eRV0bkKV4MtgIdQePc7l3pIegFtVwrg=; b=NV4DnBLHerPM1sOQKy97U/j2DtKdvGpglXtSkq1Rj0tJAKbefcerNMsJjg0s0/ZP1T UVuq+nqZyg6eNYOnKb/rS5rpVo7K/AWjXEgwGfIBSXe6ceCBAxDAQgN1gzHMwQYiAeDJ pLf/8/7fMLWemEAU1OjbvQhEMPINWQqIgdxgC/ze6p30OmB66YekVckWa7BRHwraOOdE BVlzdsFDwsK0sA0rDUFEh3Avt8AgEWZwQJ+t4VChVhDl5qA3/0ABfx2jwRqFZHrXKIjV qWmtCZbr+WBqq+92cuYjRVKCF5xhzTJQ4TU1JXlkRiZnn6aKD0tlsEhJgEYEhEoMyFt+ FSMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=CewfBZGL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w64si8742443itf.81.2018.01.23.09.06.33; Tue, 23 Jan 2018 09:06:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=CewfBZGL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751456AbeAWRE6 (ORCPT + 99 others); Tue, 23 Jan 2018 12:04:58 -0500 Received: from mail-oi0-f46.google.com ([209.85.218.46]:38724 "EHLO mail-oi0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751259AbeAWRE4 (ORCPT ); Tue, 23 Jan 2018 12:04:56 -0500 Received: by mail-oi0-f46.google.com with SMTP id m65so823509oig.5 for ; Tue, 23 Jan 2018 09:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=XRKh2JuFYYP7eRV0bkKV4MtgIdQePc7l3pIegFtVwrg=; b=CewfBZGLwnEvvKcFJzmv1GLPm2h83QeJpD6y5sypnC+OsPCNw0I54tB2T5thW061ev cRJbFil/CPMiubtt4R8KdOhJY5ORYb9xufNI3ZchhTpKyKI0Dh/VPpP+FCD8wvBdKUtW IbWbWpXHu4dLhcIaxjSuRTqgr5osE/AbKd2XtTxw7Z3LYfUHh3S1DNw95080yfu5RUJu YWufqipxX3d66q1Q14ev3/PUU0hiNs7/e9d0kcKeDj2nk8RRIdn9RQSMIXkKVhQfWEXX leH7ioMT+bvpeYdN24kNC8vmLAzs/6tBw8Ts26XVO8bSMgb1n27fhGVQeHeS66qZTjkt khKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=XRKh2JuFYYP7eRV0bkKV4MtgIdQePc7l3pIegFtVwrg=; b=pVoI/N6zfRZH8ihUNULO83ahGi1LYo3xppl7hrhrt4ZQc0fYsBdJwrgWqBuZB8kfIE IZ6rD1x8ngHpMqFOz3ji2KLmBhnodHfVh1J6HSxBSXVS93zg4Lfgm0hRI4Xb9d51fnkZ kHbd7evyXR0Ld0afJjERHEk4suSePy44xN1pULGEwEsX6mG61AQVi8pRWaGOvmnDq5uq cg8IdiKgRohox7tWHAgsuXakdDNGN2uVWWkHgm8WyYYXG4DL4qkExmVu0pc9Wy3NiZN0 T19wBsoYqdMGwrBT53owGsbFZnujF+iTYT4iddz1eNgrdc6+JNXRDffeFmdthMq4V9tz DfjQ== X-Gm-Message-State: AKwxyteE5KONOmdTRqP9/J6jWwLlowouIq9R9NOlsAGov1ar9raRXECG Q4HiQh9J523NccHfBWF1GZNjUWq6fsVURC3YAg5KZQ== X-Received: by 10.202.236.3 with SMTP id k3mr6546076oih.351.1516727095984; Tue, 23 Jan 2018 09:04:55 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.24.23 with HTTP; Tue, 23 Jan 2018 09:04:55 -0800 (PST) In-Reply-To: References: <1516468460-4908-1-git-send-email-david@lechnology.com> From: Bartosz Golaszewski Date: Tue, 23 Jan 2018 18:04:55 +0100 Message-ID: Subject: =?UTF-8?Q?Re=3A_=5BPATCH_v6_00=2F41=5D_ARM=3A_davinci=3A_convert_to_common?= =?UTF-8?Q?_clock_framework=E2=80=8B?= To: David Lechner Cc: linux-clk@vger.kernel.org, devicetree , linux-arm-kernel@lists.infradead.org, Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Bartosz Golaszewski , Adam Ford , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-01-23 17:03 GMT+01:00 David Lechner : > On 01/23/2018 08:54 AM, Bartosz Golaszewski wrote: >> >> 2018-01-22 18:30 GMT+01:00 David Lechner : >>> >>> On 01/22/2018 05:14 AM, Bartosz Golaszewski wrote: >>>> >>>> >>>> 2018-01-20 18:13 GMT+01:00 David Lechner : >>>>> >>>>> >>>>> This series converts mach-davinci to use the common clock framework. >>>>> >>>>> The series works like this, the first 19 patches create new clock >>>>> drivers >>>>> using the common clock framework. There are basically 3 groups of >>>>> clocks >>>>> - >>>>> PLL, PSC and CFGCHIP (syscon). There are six different SoCs that each >>>>> have >>>>> unique init data, which is the reason for so many patches. >>>>> >>>>> Then, starting with "ARM: da830: add new clock init using common >>>>> clock", >>>>> we get the mach code ready for the switch by adding the code needed for >>>>> the new clock drivers and adding #ifndef CONFIG_COMMON_CLK around the >>>>> legacy clocks so that we can switch easily between the old and the new. >>>>> >>>>> "ARM: davinci: switch to common clock framework" actually flips the >>>>> switch >>>>> to start using the new clock drivers. Then the next 8 patches remove >>>>> all >>>>> of the old clock code. >>>>> >>>>> The final three patches add device tree clock support to the one SoC >>>>> that >>>>> supports it. >>>>> >>>>> v6 changes (also see individual patches for details): >>>>> - All of the device tree bindings are changed >>>>> - All of the clock drivers are changed significantly >>>>> - Fixed issues brought up during review of v5 >>>>> - "ARM: davinci: move davinci_clk_init() to init_time" is removed from >>>>> this >>>>> series and submitted separately >>>>> >>>>> v5 changes: >>>>> - Basically, this is an entirely new series >>>>> - Patches are broken up into bite-sized pieces >>>>> - Converted PSC clock driver to use regmap >>>>> - Restored "force" flag for certain DA850 clocks >>>>> - Added device tree bindings >>>>> - Moved more of the clock init to drivers/clk >>>>> - Fixed frequency scaling (maybe*) >>>>> >>>>> * I have frequency scaling using cpufreq-dt, so I know the clocks are >>>>> doing >>>>> what they need to do to make this work, but I haven't figured out >>>>> how >>>>> to >>>>> test davinci-cpufreq driver yet. (Patches to make cpufreq-dt work >>>>> will >>>>> be >>>>> sent separately after this series has landed.) >>>>> >>>>> Dependencies: >>>>> >>>>> This series applies on top of linux-davinci/master plus the following >>>>> patches: >>>>> - [1] "clk: fix reentrancy of clk_enable() on UP systems" (in clk-next) >>>>> - [2] "clk: add helper functions for managing clk_onecell_data" >>>>> - [3] "clk: divider: read-only divider can propagate rate change" >>>>> - [4],[5],[6],[7],[8],[9] series "ARM: davinci: common clock prep work" >>>>> >>>> >>>> Hi David, >>>> >>>> I'm getting a splat[1] when trying to mount the rootfs over nfs on a >>>> da850-lcdk. >>>> >>>> I'll try to figure out what's happening. >>>> >>>> Best regards, >>>> Bartosz Golaszewski >>>> >>>> [1] https://pastebin.com/D94z8SAe >>>> >>> >>> Could it have something to do with the "rmii" clock? I don't think I >>> added >>> that >>> in the device tree. >>> >> >> I'm looking at it now. There are problems with emac & mdio both in >> legacy and in DT mode. > > > Adam, is networking working for you on the DA850 EVM? > >> >> The davinci_mdio driver seems to not get an actual functional clock >> (phy is reported as down). I'm seeing that in old legacy code, >> mdio_clk has emac_clk as parent, while after your changes they share >> pll0_sysclk4 as parent, although I'm not sure if that has anything to >> do with it. > > > The two clocks prior to these changes was a hack to work around a > limitation of the old lock code (because of the way it used a linked list > each clock could only be used once) so, yes, that should not have anything > to do with it. > And it was I who did the change in commit ef37427ac567 ("ARM: davinci: da850: don't add emac clock to lookup table twice") :) Already forgot that. > I see that there is no clk_prepare_enable() in the mdio driver or the emac > driver. I suppose it expects pm_runtime to take care of this maybe? > > You can see if the clock is enabled by running: > > cat /sys/kernel/debug/clk/clk_summary > >> >> I'll see about the rmii clock too. > > FWIW, the rmii clock is in the clock init for non-DT da850. > 2018-01-23 17:06 GMT+01:00 David Lechner : > On 01/23/2018 10:03 AM, David Lechner wrote: >> >> You can see if the clock is enabled by running: >> >> cat /sys/kernel/debug/clk/clk_summary >> > > I just realized if you can't boot, you can't do this. :-/ I can always boot from SD or just printk it. Thanks, Bartosz