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Subject: Re: [PATCH v2 4/5] x86/msr: Add definitions for new speculation
 control MSRs
To:     David Woodhouse <dwmw@amazon.co.uk>, arjan@linux.intel.com,
        tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org,
        linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com,
        bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com,
        ak@linux.intel.com, torvalds@linux-foundation.org,
        gregkh@linux-foundation.org, thomas.lendacky@amd.com
References: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk>
 <1516726375-25168-5-git-send-email-dwmw@amazon.co.uk>
From:   Dave Hansen <dave.hansen@intel.com>
Message-ID: <18ca2a5a-17df-e889-9c11-f5ee4c46de53@intel.com>
Date:   Tue, 23 Jan 2018 10:27:24 -0800
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On 01/23/2018 08:52 AM, David Woodhouse wrote:
> +#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
> +#define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
> +#define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */

Do we want to spell out the silly Intel acronym?  I don't know how we
fit it on the right side, but I do think we need to do it _somewhere_.
We need the code to stand on its own to some degree and not subject the
masses to reading the spec to understand the code.

/* Not to susceptible Rogue Data Cache Load aka Meltdown: */
#define ARCH_CAP_RDCL_NO		(1 << 0)