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[209.132.180.67]) by mx.google.com with ESMTP id a2si5243333itc.24.2018.01.23.10.45.13; Tue, 23 Jan 2018 10:45:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=Mra8QMlc; dkim=pass header.i=@codeaurora.org header.s=default header.b=ajHTS+fT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752371AbeAWSor (ORCPT + 99 others); Tue, 23 Jan 2018 13:44:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:36642 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752327AbeAWSoo (ORCPT ); Tue, 23 Jan 2018 13:44:44 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4F5AC6081E; Tue, 23 Jan 2018 18:44:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516733084; bh=7KDQPkaxRyoBJ9FmD/7FT2gxVxTXCgC8fAs7VCHwktE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Mra8QMlcC+n/z79i4GqkelzIQ9KlUzhILeABTWNC+kXpsQCJmiInwM9iADdhRlxcd 9AkfwiPtNL2hUImqsc2QH8266nHIQWeR4yD/ZS7GplRgveXogEH61yXFtDZ7ZY6iwU jjxDmZ2kiPBXANv/MuAZnQjNM2zwYU4QkzisJZEg= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6ED5E6032C; Tue, 23 Jan 2018 18:44:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516733083; bh=7KDQPkaxRyoBJ9FmD/7FT2gxVxTXCgC8fAs7VCHwktE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ajHTS+fTh3sN3uyg7fJwF4PtxE9efQpxSyBCDJwzOud0w21F8VU3mmAVaqAGZotEP ntHFOcmf2j4dORbWQ5ID85I4D5QX+rsy4+Ug0DaHdzZ2nrc6QT1/AJawdvGmisEotk /UlFa6o7eT9r57WiM0Lpzjv65Vp9EhxZeapKSg80= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6ED5E6032C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Tue, 23 Jan 2018 18:44:42 +0000 From: Lina Iyer To: Sudeep Holla Cc: Thomas Gleixner , Jason Cooper , Marc Zyngier , open list , linux-arm-msm@vger.kernel.org, Stephen Boyd , "Nayak, Rajendra" , asathyak@codeaurora.org Subject: Re: [PATCH RFC 0/4] irqchip: qcom: add support for PDC interrupt controller Message-ID: <20180123184442.GA12243@codeaurora.org> References: <20180123175656.11942-1-ilina@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 23 2018 at 18:15 +0000, Sudeep Holla wrote: >Hi Lina, > >On Tue, Jan 23, 2018 at 5:56 PM, Lina Iyer wrote: >> On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a >> power domain that can be powered off when not needed. Interrupts that need to >> be sensed even when the GIC is powered off, are routed through an interrupt >> controller in an always-on domain called the Power Domain Controller a.k.a PDC. >> This series adds support for the PDC's interrupt controller. >> > >Sorry for the basic questions: > >1. Will the GIC be powered off in any other state other than System suspend ? > Yes. When all the CPUs are in idle, there is an opportunity to power off the CPU's power domain and the GIC. QCOM SoCs have been doing that for many generations now. >2. Why this needs to be done in Linux, why can't it be transparent and hidden > in the firmware doing the actual GIC power down ? I assume Linux is not > powering down the GIC. No. You are right, Linux is not powering off the GIC directly. A dedicated processor for power management in the SoC does that. Platform drivers in Linux, know and configure the wakeup interrupts (depending on the usecase). This is runtime specific and this is the way to tell the SoC to wake up the processor even if the GIC and the CPU domain were powered off. > >3. I see some bits that enable secure interrupts in one of the patch. >Is that even > safe to allow Linux to enable some secure interrupts in PDC ? > Linux should not and would not configure secure interrupts. We would not have permissions for secure interrupts. The interrupt names might be a misnomer, but the interrupts listed in patch #4 are all non-secure interrupts. Thanks, Lina