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[209.132.180.67]) by mx.google.com with ESMTP id g4-v6si5633372pll.464.2018.01.23.21.49.43; Tue, 23 Jan 2018 21:49:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GIMVu8LL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752281AbeAXFsF (ORCPT + 99 others); Wed, 24 Jan 2018 00:48:05 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:34117 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751081AbeAXFsD (ORCPT ); Wed, 24 Jan 2018 00:48:03 -0500 Received: by mail-pg0-f66.google.com with SMTP id r19so2000569pgn.1 for ; Tue, 23 Jan 2018 21:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2Vkrw4xD71MYlSvVhUHhv+OTgRUTz6vaawMm4YNkoPI=; b=GIMVu8LLdeky1ITAK/tDJlxcASNxAkZIsz8huRWwy0r3/NI1tUY9f4X9HpyXfd8JQg po9MYRUfp5v8VJe5IwFgXn9Eu0eYB5zs5ORtO8VE7ABkRGCv0ZhtlnJKJBNJu5Jf3BF8 jRtNtp5Nht8lJzzV5z2KWe9ClDNGIFIVG8An8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2Vkrw4xD71MYlSvVhUHhv+OTgRUTz6vaawMm4YNkoPI=; b=qPshrm4jmCDBCe+YeQFJPzMsyF1KfmSOXtb3pyWmysaCK1E3so4t9lOnscTe9lx1A2 1atXKP2rwRrpj7t6zJDt/aDXtLXhqbx1cAwKM6kKwWY5LMMXoTQ/jvuTc59e5Ul7X49C DSZwUXMFl6KquDxQZKd2FCwZ6h8EqeYMlYKf28IwsCQ/fDMDt2Ga05Q4sUcq9Yf8vRjD DfCXsqHXeiy5qVaHDkQvOleBbVBgxQGeXcNRWZGVmS7qoLMlJVqhGG9IsxKD0yqIQJmT f7Kr7KezULTT5SuA+eaK+IIlWogz61wkoml5YiSPcuZRCpgdr09eTr0hwI6pEGxKYcFb sp8A== X-Gm-Message-State: AKwxytfPYfnJKkMEzfQZELWCKoaxY49UnaW1t/ZsKJpp3x3RcDZpHljC LxVcU3Lykv8LcxcGqoxrqdJR3g== X-Received: by 10.101.78.141 with SMTP id b13mr8416902pgs.286.1516772882702; Tue, 23 Jan 2018 21:48:02 -0800 (PST) Received: from localhost.localdomain ([45.56.152.94]) by smtp.gmail.com with ESMTPSA id f188sm8524519pfc.22.2018.01.23.21.47.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jan 2018 21:48:02 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, project-aspen-dev@linaro.org, Shawn Guo Subject: [PATCH v5 RESEND 0/3] Add Combo PHY driver for HiSilicon STB SoCs Date: Wed, 24 Jan 2018 13:47:34 +0800 Message-Id: <1516772857-3580-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kishon, This is a resend of v5 [1], which has been there for a quite a while. I rebased it on next-20180119. Please let me know if you have any comments. [1] https://patchwork.ozlabs.org/cover/832088/ Shawn It adds device tree bindings and driver support for Combo PHY device which can be found on HiSilicon STB SoCs. Changes for v5: - Add bindings doc for Hi3798CV200 peripheral controller, and refer to the bindings of this parent node in combphy bindings doc. Changes for v4: - Instead of relying on device id, add a new property hisilicon,fixed-mode for combphy device that doesn't support mode select but a fixed phy mode. - Move combphy mode select register bits definition to device tree, as it may vary from one device to another. Changes for v3: - Make combphy device be child of peripheral controller and use 'reg' property for mapping combphy configuration registers. - Kill "hisilicon,peripheral-syscon" property, since parent node is just the syscon controller now. - Check combphy id to handle the quirk that combphy0 can not configure mode but always works in USB3 mode. - Unify phy .init and .exit hooks for different combphy instances and work modes, as the only quirk we need to handle is that combphy0 can only work in USB3 mode. - Better naming for clock and reset, 'ref' to 'ref_clk', 'por' to 'por_rst'. Changes for v2: - Move DT bindings into a separate patch. - Drop the spurious newline from drivers/phy/Makefile. - Use the phy type defines in dt-bindings/phy/phy.h. - Use PTR_ERR_OR_ZERO() for checking return from devm_of_phy_provider_register(). - Add USB3 phy support. Jianguo Sun (2): dt-bindings: add bindings doc for hi3798cv200 combphy phy: add combo phy driver for HiSilicon STB SoCs Shawn Guo (1): dt-bindings: hisilicon: add doc for Hi3798CV200 peripheral controller .../bindings/arm/hisilicon/hisilicon.txt | 23 ++ .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 +++++ drivers/phy/hisilicon/Kconfig | 9 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-histb-combphy.c | 289 +++++++++++++++++++++ 5 files changed, 381 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt create mode 100644 drivers/phy/hisilicon/phy-histb-combphy.c -- 1.9.1