Received: by 10.223.176.46 with SMTP id f43csp703397wra; Wed, 24 Jan 2018 04:47:11 -0800 (PST) X-Google-Smtp-Source: AH8x225EmN3z/YMQ9l+NaqIdIvFn8Vp1X7Tmh08s4Z2J3G3XqsBhDGHC1Sjo2WLSIgA/Zr+B7rQp X-Received: by 10.101.96.207 with SMTP id r15mr10690853pgv.139.1516798031467; Wed, 24 Jan 2018 04:47:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516798031; cv=none; d=google.com; s=arc-20160816; b=sEdVYSs0EImNAmsxGMvcYvCVVarqbK/VtS6ElxrJFAVgGqZEqsWr1Kxj90cArDPE7p C+A7FqLqParBU4nQXhNAAbQJE+xnLrWlrwxSqyyD3WPmWakhOc0H5zmB/mIPcxHEjOB5 x3qFiaLA8YgPgLFrOkFO6Rw2y1A6Kvo4YozD25lmnhqWnN6qXjTVuoWFj+U6ezVKYe5r 9BE7TWalsIgimDzy2BNrRsBMWp/5iif1Su2h0t7kjTDc6NugtumYBUDTMpNxfvx9LFpv ubt5nG1cBVa58rX2Vthd5n8WzqNKD/YDaia7TQxpmuQWkqRKIU7jmDsd72dIScpRjc76 mYxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-disposition :content-transfer-encoding:mime-version:robot-unsubscribe:robot-id :git-commit-id:subject:to:references:in-reply-to:reply-to:cc :message-id:from:date:arc-authentication-results; bh=Exl/fGStwWZ32X/nXr5b2/tr6ZPGXnad7Nk4Cl/4xgQ=; b=gE/dBWpYQb4PwDItNtqbeJ1cpMkoq17MwlP1+Gidta2ubsNV4tyxPx+Q2KEdvHWLc9 h4M5uP8elq1X62jjeKHXShKU85RadXmsVfRt7gb7NQeDqhNI8M+F+pr9H7GImycTTBxb hlAm8xouO3l+7jO4lpKpFWIepeJskK/LOFQfGG5y+lOdB5WYHZlB5zgpfFrJjGmH6zSD gRa/DZIggEIqOCuuSOnGYJZzVAlJzkAwb3uOOTc1N90CIrevjCxbgK12EFk4RGOhgyvE diADhLa7qgFWFnOYAhIEjK98RgXY2vdJFUL8mPvS93X4zNceSg+OXsu4z5EMIoLaWz/U qg3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e1-v6si167001pln.165.2018.01.24.04.46.57; Wed, 24 Jan 2018 04:47:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933643AbeAXMoQ (ORCPT + 99 others); Wed, 24 Jan 2018 07:44:16 -0500 Received: from terminus.zytor.com ([65.50.211.136]:52021 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933397AbeAXMoN (ORCPT ); Wed, 24 Jan 2018 07:44:13 -0500 Received: from terminus.zytor.com (localhost [127.0.0.1]) by terminus.zytor.com (8.15.2/8.15.2) with ESMTP id w0OCh4eq023286; Wed, 24 Jan 2018 04:43:04 -0800 Received: (from tipbot@localhost) by terminus.zytor.com (8.15.2/8.15.2/Submit) id w0OCh3De023283; Wed, 24 Jan 2018 04:43:03 -0800 Date: Wed, 24 Jan 2018 04:43:03 -0800 X-Authentication-Warning: terminus.zytor.com: tipbot set sender to tipbot@zytor.com using -f From: tip-bot for davidwang Message-ID: Cc: tglx@linutronix.de, mingo@kernel.org, hpa@zytor.com, linux-kernel@vger.kernel.org, davidwang@zhaoxin.com Reply-To: linux-kernel@vger.kernel.org, davidwang@zhaoxin.com, mingo@kernel.org, hpa@zytor.com, tglx@linutronix.de In-Reply-To: <1516616057-5158-1-git-send-email-davidwang@zhaoxin.com> References: <1516616057-5158-1-git-send-email-davidwang@zhaoxin.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/timers] x86/centaur: Mark TSC invariant Git-Commit-ID: fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham autolearn_force=no version=3.4.1 X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on terminus.zytor.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d Gitweb: https://git.kernel.org/tip/fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d Author: davidwang AuthorDate: Mon, 22 Jan 2018 18:14:17 +0800 Committer: Thomas Gleixner CommitDate: Wed, 24 Jan 2018 13:38:10 +0100 x86/centaur: Mark TSC invariant Centaur CPU has a constant frequency TSC and that TSC does not stop in C-States. But because the corresponding TSC feature flags are not set for that CPU, the TSC is treated as not constant frequency and assumed to stop in C-States, which makes it an unreliable and unusable clock source. Setting those flags tells the kernel that the TSC is usable, so it will select it over HPET. The effect of this is that reading time stamps (from kernel or user space) will be faster and more efficent. Signed-off-by: davidwang Signed-off-by: Thomas Gleixner Cc: qiyuanwang@zhaoxin.com Cc: linux-pm@vger.kernel.org Cc: brucechang@via-alliance.com Cc: cooperyan@zhaoxin.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1516616057-5158-1-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/centaur.c | 4 ++++ drivers/acpi/processor_idle.c | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 68bc6d9..c578cd2 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -106,6 +106,10 @@ static void early_init_centaur(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSENTER32); #endif + if (c->x86_power & (1 << 8)) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } } static void init_centaur(struct cpuinfo_x86 *c) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index d50a7b6..5f0071c 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -207,6 +207,7 @@ static void tsc_check_state(int state) switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: case X86_VENDOR_INTEL: + case X86_VENDOR_CENTAUR: /* * AMD Fam10h TSC will tick in all * C/P/S0/S1 states when this bit is set.