Received: by 10.223.176.46 with SMTP id f43csp1005170wra; Wed, 24 Jan 2018 09:08:20 -0800 (PST) X-Google-Smtp-Source: AH8x226q1+//FoIuiakRroFMdBiMLuqfOfOkcajlt3acY9A9EWlvNTjSsgw2U7vrRhgf8IW7Oj9s X-Received: by 2002:a17:902:14d:: with SMTP id 71-v6mr8835614plb.42.1516813700152; Wed, 24 Jan 2018 09:08:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516813700; cv=none; d=google.com; s=arc-20160816; b=nGgh44OanlROl/+E6PS6eokPkU3ZHNVQGBUIkz8Ug+AGawnFcSexQjHKmChpIdNZLl 1eeCFII5gPABcmC3lxZl2RE+x91ehXu5mFNlt7YDTYOGcP8e2lIZ7g1h4XKovn34wsoN r6XAOUoDBKqA11k5hdyywOuJzIz0rg3FoSIyXWDIdz2bK7D5mDGIcTI9hEH74yDpfyzu cYNFRHctmwnV7DYaIG75BRc8udgLfhe4TJu5OdB8IldiYbbdOB5HMczlTuJtUBW1G0GC EWm8hTn6a6yTygAEfl2wHJek9wnG1Nsxy+NTE3uzHAilhz+CP2ERi0foqGPjdAe1A0LH Ui9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date:arc-authentication-results; bh=s6sFy7TNK0BaZYZUKHxyLpT+RVFW+uWWcK+B4bwKdjw=; b=M5D5PN0wG6/V/hMWk1CqZ7jvmDPsaMQQmpff0UPZm+v9p0Bui2FnD9jmYpcPXhkWAF Pb04w7oAbxVxFeAoVlAz0s1a1qrp2/nKCa45bysFiJeAA4LXlpOAwbe0NR0Qvp3Y4z5h INGc3FmPr9mPaLPQV/0GiJtEr6gzjgaET+2V+zOu+OKpikBoNeoHOv4cw541liXE1eWC Av0306kMAHgeldmlrCUxxgxc+L2crx3B+kgREKYfo2aUD8REB0oKZrzO6EMXT/FUJ1Aw 7SHQ0+wdGnm5jALhpC73IBt/fip8M/XN2VYD/jmLoYZ+BfWnWER8ZW7lHa4GQTpv8chB W/yQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q1-v6si447374plr.772.2018.01.24.09.08.06; Wed, 24 Jan 2018 09:08:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964890AbeAXRHd convert rfc822-to-8bit (ORCPT + 99 others); Wed, 24 Jan 2018 12:07:33 -0500 Received: from www.llwyncelyn.cymru ([82.70.14.225]:35894 "EHLO fuzix.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964791AbeAXRHb (ORCPT ); Wed, 24 Jan 2018 12:07:31 -0500 Received: from alans-desktop (82-70-14-226.dsl.in-addr.zen.co.uk [82.70.14.226]) by fuzix.org (8.15.2/8.15.2) with ESMTP id w0OH748U010812; Wed, 24 Jan 2018 17:07:04 GMT Date: Wed, 24 Jan 2018 17:07:03 +0000 From: Alan Cox To: David Woodhouse Cc: Dave Hansen , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/5] x86/pti: Do not enable PTI on fixed Intel processors Message-ID: <20180124170652.4c78ca17@alans-desktop> In-Reply-To: <1516811127.13558.150.camel@infradead.org> References: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk> <1516726375-25168-6-git-send-email-dwmw@amazon.co.uk> <20180123173312.1d8cf02f@alans-desktop> <1516811127.13558.150.camel@infradead.org> Organization: Intel Corporation X-Mailer: Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >   > +static const __initdata struct x86_cpu_id cpu_no_meltdown[] = { > + { X86_VENDOR_AMD }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, As Linus said this should be no_specualtion[] If we are going to capture 32bit here with your lines below I'll send you an update at some point with all the 32bit families hunted down (some like the CE4100 may take a bit of hunting) > + { X86_VENDOR_ANY, 5 }, AND K5 speculates, Cyrix 6x86 speculates, IDT WinChip does not. I think this should be X86_VENDOR_ANY, 4 X86_VENDOR_INTEL, 5, X86_VENDOR_CENTAUR, 5, > +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c) > +{ > + u64 ia32_cap = 0; > + > + if (x86_match_cpu(cpu_no_meltdown)) > +                return false; These processors are also not vulnerable to spectre, so this patch doesn't set the other flags correctly - that's why we need two levels of logic here. "Bonnell" and "Saltwell" uarch Atom processors are not vulnerable to Meltdown or Spectre, neithr is a 486, Pentium, Quark etc. > + > + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); > + if (ia32_cap & ARCH_CAP_RDCL_NO) > + return false; > + > + return true; > +} > + >  /* >   * Do minimum CPU detection early. >   * Fields really needed: vendor, cpuid_level, family, model, mask, > @@ -900,9 +929,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) >   >   setup_force_cpu_cap(X86_FEATURE_ALWAYS); >   > - if (c->x86_vendor != X86_VENDOR_AMD) > + if (early_cpu_vulnerable_meltdown(c)) >   setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); > - >   setup_force_cpu_bug(X86_BUG_SPECTRE_V1); >   setup_force_cpu_bug(X86_BUG_SPECTRE_V2); >   > --  > 2.14.3