Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Wed, 24 Jan 2018 10:09:00 -0800
From:   Brian Norris <briannorris@chromium.org>
To:     Philippe CORNU <philippe.cornu@st.com>
Cc:     Archit Taneja <architt@codeaurora.org>,
        Andrzej Hajda <a.hajda@samsung.com>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        David Airlie <airlied@linux.ie>,
        Benjamin Gaignard <benjamin.gaignard@linaro.org>,
        Bhumika Goyal <bhumirks@gmail.com>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Sandy Huang <hjc@rock-chips.com>,
        Heiko Stubner <heiko@sntech.de>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-rockchip@lists.infradead.org" 
        <linux-rockchip@lists.infradead.org>,
        Yannick FERTRE <yannick.fertre@st.com>,
        Vincent ABRIOU <vincent.abriou@st.com>,
        Alexandre TORGUE <alexandre.torgue@st.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Ludovic BARRE <ludovic.barre@st.com>,
        Mickael REULIER <mickael.reulier@st.com>,
        "hl@rock-chips.com" <hl@rock-chips.com>,
        Chris Zhong <zyw@rock-chips.com>,
        "nickey.yang@rock-chips.com" <nickey.yang@rock-chips.com>
Subject: Re: [PATCH v3] drm/bridge/synopsys: dsi: add optional pixel clock
Message-ID: <20180124180859.mr736rpzysq5vn54@ban.mtv.corp.google.com>
References: <20180123170806.5282-1-philippe.cornu@st.com>
 <20180123204939.qirvr34mlwgiwmqz@ban.mtv.corp.google.com>
 <507552a3-c68f-d6ac-a747-b8f5168d0d41@st.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <507552a3-c68f-d6ac-a747-b8f5168d0d41@st.com>
User-Agent: NeoMutt/20170609 (1.8.3)
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Wed, Jan 24, 2018 at 09:24:06AM +0000, Philippe CORNU wrote:
> On 01/23/2018 09:49 PM, Brian Norris wrote:
> > On Tue, Jan 23, 2018 at 06:08:06PM +0100, Philippe Cornu wrote:
> >> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> >> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

> >> @@ -828,6 +833,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> >>   		return ERR_PTR(ret);
> >>   	}
> >>   
> >> +	dsi->px_clk = devm_clk_get(dev, "px_clk");
> > 
> > Did you write a device tree binding document update for this anywhere?
> 
> Many thanks for your review,
> 
> yes, "px_clk" is already documented, please have a look to 
> Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

Ah, I see. Normally I expect that the binding document is sent around
when the first user of it shows up, but I guess that's not a
requirement. Sorry I missed that!

Just a note: I don't think that Rockchip systems have an equivalent
clock from which to directly derive the pixel clock rate. I believe it's
controlled through additional dividers that are not part of the common
clock framework. So this isn't particularly useful for them.

I don't think it's worth very much in this case, but:

Reviewed-by: Brian Norris <briannorris@chromium.org>