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Date:   Wed, 24 Jan 2018 18:26:42 +0000
From:   Alan Cox <gnomes@lxorguk.ukuu.org.uk>
To:     TimGuo <timguo@zhaoxin.com>
Cc:     <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>,
        <mingo@kernel.org>, <x86@kernel.org>, <linux-pm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <brucechang@via-alliance.com>,
        <cooperyan@zhaoxin.com>, <qiyuanwang@zhaoxin.com>,
        <benjaminpan@viatech.com>
Subject: Re: [PATCH] x86/centaur: Mark TSC invariant
Message-ID: <20180124182642.0669c9bd@alans-desktop>
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On Mon, 15 Jan 2018 09:35:45 +0800
TimGuo <timguo@zhaoxin.com> wrote:

> Centaur CPU has a constant frequency TSC and that TSC does not stop in C-States.
> But because the flags are not set for that CPU, the TSC is treated as non constant
> frequency and assumed to stop in C-States, which makes it an unreliable and unusable
> clock source. Setting those flags tells the kernel that the TSC is usable, so it
> will select it over HPET. The effect of this is that reading time stamps (from kernel
> or userspace) will be faster and more efficient.

And this is true for all processors back to  IDT WinChip ?

Alan