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[209.132.180.67]) by mx.google.com with ESMTP id z3-v6si34160plo.815.2018.01.24.19.09.11; Wed, 24 Jan 2018 19:09:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=Y5ACHQl5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933313AbeAYDIR (ORCPT + 99 others); Wed, 24 Jan 2018 22:08:17 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34245 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932906AbeAYDIO (ORCPT ); Wed, 24 Jan 2018 22:08:14 -0500 Received: by mail-pf0-f195.google.com with SMTP id e76so4777565pfk.1 for ; Wed, 24 Jan 2018 19:08:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=QaJA9NOufW97yCo/bC1C8J5lBvLppozK81jqRWJuXlY=; b=Y5ACHQl5URfzJVl6wx1mbfWMBeHvLizqWChPr2bMR4cIFCX+XEImhgeFu8qF8SNFYC SuzyjHk4PWoZN5m8AlQWijlktJMhzB03qhj9IdLMBPeb7z+ajrNIAMibl5mqPbr3szms 32dABGWbXhuk74z5hrewWXY/gnZoJRQTc1PhLETWJ9ztz0gk5j+cJ4isY29Q5mjGXQKT /310HIWAdlRCzVXPb5LlzDQcMvJZ5UoFbSh7daM3qHQcSNiug169bN+3W1eQ4edCYttl V1BVdt76hrt5nMtcyWji9yLNyWXAaJIExwTt/LMa0YHXGGYQ/Fi/Zf2lPd57e8LRXW3d cEGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=QaJA9NOufW97yCo/bC1C8J5lBvLppozK81jqRWJuXlY=; b=rj55oipfBalkjbN9D/G8Bi3STYIJ6Ab3QVhVUycr8mnTgELXB4trNiQHyNSdthjfj1 GtOve9r8ygiO7nRPn3Kmc2IPAx5CtkQV19NPVXO5DAWJyYoTHNJ05h8YiPKsbR3d0r6o taONtv5sR526bVM14EUScwPF4I3LrNGqtCKv7Cs8HfdNqPfIyNQWzXkLuVbFNOmYXZoU ZUQ6HGODqOfhXSvGiCaHmDllhkLV1aytUrsI7APKwqeTxXu66n3NbEDxGyypYXy5eSeC M2kXP7gtkljtVJuNEs578y1yIkEsYsMUvyZahlvsp+LVu6KOChY266LGVVhpCUZZVz2L X8Fw== X-Gm-Message-State: AKwxyteLOBgOR2M4WCTFG030MIsKZOe0UvIHU8RdERw4N3uj4XaNv5Zq QGduRQDSQqDD1mCzkGh9bi8kWsGFAWw= X-Received: by 2002:a17:902:1a2:: with SMTP id b31-v6mr9173507plb.28.1516849693713; Wed, 24 Jan 2018 19:08:13 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id m67sm11306163pfi.157.2018.01.24.19.08.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2018 19:08:13 -0800 (PST) Subject: [PATCH v2 1/4] arm: Make set_handle_irq and handle_arch_irq generic Date: Wed, 24 Jan 2018 19:07:53 -0800 Message-Id: <20180125030756.21787-2-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180125030756.21787-1-palmer@sifive.com> References: <20180125030756.21787-1-palmer@sifive.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, patches@groups.riscv.org, Palmer Dabbelt From: Palmer Dabbelt To: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, tglx@linutronix.de, Christoph Hellwig , Arnd Bergmann Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It looks like this same irqchip registration mechanism has been copied into a handful of ports, including aarch64 and openrisc. I want to use this in the RISC-V port, so I thought it would be good to make this generic instead. This patch simply moves set_handle_irq and handle_arch_irq from arch/arm to kernel/irq/handle.c. Signed-off-by: Palmer Dabbelt --- arch/arm/Kconfig | 5 ----- arch/arm/include/asm/irq.h | 5 ----- arch/arm/kernel/entry-armv.S | 6 ------ arch/arm/kernel/irq.c | 10 ---------- include/linux/irq.h | 18 ++++++++++++++++++ kernel/irq/Kconfig | 5 +++++ kernel/irq/handle.c | 10 ++++++++++ 7 files changed, 33 insertions(+), 26 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 51c8df561077..e51f907668f6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -917,11 +917,6 @@ config IWMMXT Enable support for iWMMXt context switching at run time if running on a CPU that supports it. -config MULTI_IRQ_HANDLER - bool - help - Allow each machine to specify it's own IRQ handler at run time. - if !MMU source "arch/arm/Kconfig-nommu" endif diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index b6f319606e30..c883fcbe93b6 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -31,11 +31,6 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); -#ifdef CONFIG_MULTI_IRQ_HANDLER -extern void (*handle_arch_irq)(struct pt_regs *); -extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); -#endif - #ifdef CONFIG_SMP extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index fbc707626b3e..2d31cec2f4cb 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -1230,9 +1230,3 @@ vector_addrexcptn: .globl cr_alignment cr_alignment: .space 4 - -#ifdef CONFIG_MULTI_IRQ_HANDLER - .globl handle_arch_irq -handle_arch_irq: - .space 4 -#endif diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index ece04a457486..9908dacf9229 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -102,16 +102,6 @@ void __init init_IRQ(void) uniphier_cache_init(); } -#ifdef CONFIG_MULTI_IRQ_HANDLER -void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) -{ - if (handle_arch_irq) - return; - - handle_arch_irq = handle_irq; -} -#endif - #ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs(void) { diff --git a/include/linux/irq.h b/include/linux/irq.h index a0231e96a578..4e7ca0216fb9 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1170,4 +1170,22 @@ int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); int ipi_send_single(unsigned int virq, unsigned int cpu); int ipi_send_mask(unsigned int virq, const struct cpumask *dest); +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Registers a generic IRQ handling function as the top-level IRQ handler in + * the system, which is generally the first C code called from an assembly + * architecture-specific interrupt handler. + * + * Returns 0 on success, or -EBUSY if an IRQ handler has already been + * registered. + */ +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); + +/* + * Allows interrupt handlers to find the irqchip that's been registered as the + * top-level IRQ handler. + */ +extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; +#endif + #endif /* _LINUX_IRQ_H */ diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index 89e355866450..1b84dccd1a03 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -142,3 +142,8 @@ config GENERIC_IRQ_DEBUGFS If you don't know what to do here, say N. endmenu + +config MULTI_IRQ_HANDLER + bool + help + Allow each machine to specify it's own IRQ handler at run time. diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index 79f987b942b8..eb55650a2abc 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -20,6 +20,8 @@ #include "internals.h" +void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; + /** * handle_bad_irq - handle spurious and unhandled irqs * @desc: description of the interrupt @@ -207,3 +209,11 @@ irqreturn_t handle_irq_event(struct irq_desc *desc) irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); return ret; } + +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) +{ + if (handle_arch_irq) + return; + + handle_arch_irq = handle_irq; +} -- 2.13.6