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[209.132.180.67]) by mx.google.com with ESMTP id p17si1341151pgq.161.2018.01.25.01.24.19; Thu, 25 Jan 2018 01:24:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=pfdeQ1Fn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751504AbeAYJXh (ORCPT + 99 others); Thu, 25 Jan 2018 04:23:37 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:39574 "EHLO smtp-fw-9102.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751411AbeAYJXe (ORCPT ); Thu, 25 Jan 2018 04:23:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1516872214; x=1548408214; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=tBNZZ1zDUwiJm1OmYzEGmIUCJsnc/RyHj6+aqsOtrWo=; b=pfdeQ1Fnjfthynvc9ucdxtBxCJQ2dicU7oCx4QEseNcFlg54rBXeqqIK fDBbBDeyGEav0FWyTA1WMUH36NBjNVQNc6IfQuM96SqjekMJYG5t82a0+ gM8jjPXE7OD22VgDTFKyyi6QTOJxQuLX3IQ279zJY4HRk/qnYIxiUjdeZ c=; X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="589777905" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-1e-97fdccfd.us-east-1.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 25 Jan 2018 09:23:31 +0000 Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (iad1-ws-svc-lb91-vlan3.amazon.com [10.0.103.150]) by email-inbound-relay-1e-97fdccfd.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w0P9NKq8110551 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 25 Jan 2018 09:23:23 GMT Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (localhost [127.0.0.1]) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w0P9NHKs017423; Thu, 25 Jan 2018 09:23:17 GMT Received: (from dwmw@localhost) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Submit) id w0P9NDdL017417; Thu, 25 Jan 2018 09:23:13 GMT From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 0/7] Basic Speculation Control feature support Date: Thu, 25 Jan 2018 09:23:02 +0000 Message-Id: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the basic CPUID and MSR definitions for AMD and Intel, followed by the complete no-brainer: Disable KPTI on Intel CPUs which set the RDCL_NO bit to say that they don't need it, as well as others which are known not to speculate such as old Atoms and even older 32-bit chips. Alan will continue an archæological dig to round up some more entries for that table. Also blacklist the early Intel microcodes for Spectre mitigation features, and add the basic support for indirect_branch_prediction_barrier(). The latter is needed to protect userspace and complete the retpoline-based mitigation. Patches on top of it are being bikeshedded as we speak... v2: Cleanups, add AMD bits for STIBP/SPEC_CTRL. v3: Add more CPUs to the exemption for KPTI and clean that up. Add microcode blacklist (RFC). v4: Roll in 'no speculation' list for CPUs not vulnerable to Spectre. Cosmetic cleanups in microcode blacklist table. David Woodhouse (7): x86/cpufeatures: Add CPUID_7_EDX CPUID leaf x86/cpufeatures: Add Intel feature bits for Speculation Control x86/cpufeatures: Add AMD feature bits for Speculation Control x86/msr: Add definitions for new speculation control MSRs x86/pti: Do not enable PTI on processors which are not vulnerable to Meltdown x86/cpufeature: Blacklist SPEC_CTRL on early Spectre v2 microcodes x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support arch/x86/include/asm/cpufeature.h | 7 +++- arch/x86/include/asm/cpufeatures.h | 15 +++++-- arch/x86/include/asm/disabled-features.h | 3 +- arch/x86/include/asm/msr-index.h | 12 ++++++ arch/x86/include/asm/nospec-branch.h | 13 ++++++ arch/x86/include/asm/required-features.h | 3 +- arch/x86/kernel/cpu/bugs.c | 7 ++++ arch/x86/kernel/cpu/common.c | 48 ++++++++++++++++++--- arch/x86/kernel/cpu/intel.c | 71 ++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/scattered.c | 2 - 10 files changed, 167 insertions(+), 14 deletions(-) -- 2.7.4