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Date:   Thu, 25 Jan 2018 10:42:58 +0100
From:   Peter Zijlstra <peterz@infradead.org>
To:     David Woodhouse <dwmw@amazon.co.uk>
Cc:     arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de,
        x86@kernel.org, linux-kernel@vger.kernel.org,
        tim.c.chen@linux.intel.com, bp@alien8.de, pbonzini@redhat.com,
        ak@linux.intel.com, torvalds@linux-foundation.org,
        gregkh@linux-foundation.org, dave.hansen@intel.com,
        gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org
Subject: Re: [PATCH v4 5/7] x86/pti: Do not enable PTI on processors which
 are not vulnerable to Meltdown
Message-ID: <20180125094258.GZ2228@hirez.programming.kicks-ass.net>
References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk>
 <1516872189-16577-6-git-send-email-dwmw@amazon.co.uk>
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On Thu, Jan 25, 2018 at 09:23:07AM +0000, David Woodhouse wrote:
> +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c)
> +{
> +	u64 ia32_cap = 0;
> +
> +	if (x86_match_cpu(cpu_no_meltdown))
> +                return false;
> +
> +	if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> +		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);

I think it was suggested a while back to write this like:

	if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES) &&
	    !rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, ia32_cap))

to deal with funny virt scenarios where they accidentally advertise the
CPUID bit but don't in fact provide the MSR.

> +
> +	/* Rogue Data Cache Load? No! */
> +	if (ia32_cap & ARCH_CAP_RDCL_NO)
> +		return false;
> +
> +	return true;
> +}