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[209.132.180.67]) by mx.google.com with ESMTP id r10si1542037pgd.329.2018.01.25.04.57.14; Thu, 25 Jan 2018 04:57:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbeAYMn4 convert rfc822-to-8bit (ORCPT + 99 others); Thu, 25 Jan 2018 07:43:56 -0500 Received: from smtp-out4.electric.net ([192.162.216.195]:54022 "EHLO smtp-out4.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752071AbeAYMny (ORCPT ); Thu, 25 Jan 2018 07:43:54 -0500 Received: from 1eegsa-00045k-U2 by out4c.electric.net with emc1-ok (Exim 4.87) (envelope-from ) id 1eegsh-0004YJ-T5; Thu, 25 Jan 2018 04:43:51 -0800 Received: by emcmailer; Thu, 25 Jan 2018 04:43:50 -0800 Received: from [156.67.243.126] (helo=AcuMS.aculab.com) by out4c.electric.net with esmtps (TLSv1.2:ECDHE-RSA-AES256-SHA384:256) (Exim 4.87) (envelope-from ) id 1eegsa-00045k-U2; Thu, 25 Jan 2018 04:43:44 -0800 Received: from AcuMS.Aculab.com (fd9f:af1c:a25b:0:43c:695e:880f:8750) by AcuMS.aculab.com (fd9f:af1c:a25b:0:43c:695e:880f:8750) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 25 Jan 2018 12:44:34 +0000 Received: from AcuMS.Aculab.com ([fe80::43c:695e:880f:8750]) by AcuMS.aculab.com ([fe80::43c:695e:880f:8750%12]) with mapi id 15.00.1347.000; Thu, 25 Jan 2018 12:44:34 +0000 From: David Laight To: 'Will Deacon' , Mark Salter CC: Marc Zyngier , Khuong Dinh , "linux-arm-kernel@lists.infradead.org" , "catalin.marinas@arm.com" , "jcm@redhat.com" , "lorenzo.pieralisi@arm.com" , "ard.biesheuvel@linaro.org" , "linux-kernel@vger.kernel.org" , "christoffer.dall@linaro.org" , "patches@apm.com" Subject: RE: [PATCH] arm64: turn off xgene branch prediction while in kernel space Thread-Topic: [PATCH] arm64: turn off xgene branch prediction while in kernel space Thread-Index: AQHTlTKUZVrNGkpW6UiZL00ACo1uxaOEiUrQ Date: Thu, 25 Jan 2018 12:44:34 +0000 Message-ID: <13f48247088a49b0a4a9afef0aa576a7@AcuMS.aculab.com> References: <1516760007-14670-1-git-send-email-kdinh@apm.com> <1516811703.2957.47.camel@redhat.com> <20180124164324.GA30462@arm.com> In-Reply-To: <20180124164324.GA30462@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.33] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-Outbound-IP: 156.67.243.126 X-Env-From: David.Laight@ACULAB.COM X-Proto: esmtps X-Revdns: X-HELO: AcuMS.aculab.com X-TLS: TLSv1.2:ECDHE-RSA-AES256-SHA384:256 X-Authenticated_ID: X-PolicySMART: 3396946, 3397078 X-Virus-Status: Scanned by VirusSMART (c) X-Virus-Status: Scanned by VirusSMART (s) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Will Deacon > Sent: 24 January 2018 16:43 > On Wed, Jan 24, 2018 at 11:35:03AM -0500, Mark Salter wrote: > > On Wed, 2018-01-24 at 10:58 +0000, Marc Zyngier wrote: > > > Khuong, > > > > > > On 24/01/18 02:13, Khuong Dinh wrote: > > > > Aliasing attacks against CPU branch predictors can allow an attacker to > > > > redirect speculative control flow on some CPUs and potentially divulge > > > > information from one context to another. > > > > > > > > This patch only supports for XGene processors. ... > > > Why isn't this using the infrastructure that is already in place? > > > > That infrastructure relies on a cpu-specific flush of the branch > > predictor. XGene does not have the ability to flush the branch > > predictor. It can only turn it on or off. > > So how does this patch protect one user application from another? Sounds > like you need to turn the thing off at boot and leave it that way, or find > a sequence of branch instructions to effectively do the invalidation. What sort of performance penalty does this give? I can imagine it is significant. Attempting to flush a branch predictor is also likely to be very slow. David