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[209.132.180.67]) by mx.google.com with ESMTP id 37-v6si2082034plc.215.2018.01.25.06.38.06; Thu, 25 Jan 2018 06:38:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751511AbeAYOOS (ORCPT + 99 others); Thu, 25 Jan 2018 09:14:18 -0500 Received: from relay2-d.mail.gandi.net ([217.70.183.194]:60255 "EHLO relay2-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751312AbeAYOOP (ORCPT ); Thu, 25 Jan 2018 09:14:15 -0500 Received: from w540 (unknown [IPv6:2001:b07:6442:1ac4:c4b5:434a:5a04:9386]) (Authenticated sender: jacopo@jmondi.org) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id A40F7C5A4E; Thu, 25 Jan 2018 15:14:09 +0100 (CET) Date: Thu, 25 Jan 2018 15:14:07 +0100 From: jacopo mondi To: Geert Uytterhoeven Cc: Jacopo Mondi , Magnus Damm , Kuninori Morimoto , Laurent Pinchart , Yoshinori Sato , Rich Felker , Linux-sh list , Linux-Renesas , Linux Media Mailing List , Linux Kernel Mailing List , linux-clk Subject: Re: [PATCH] sh: clk: Relax clk rate match test Message-ID: <20180125141407.GH17416@w540> References: <1516879493-24637-1-git-send-email-jacopo+renesas@jmondi.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Thu, Jan 25, 2018 at 02:53:41PM +0100, Geert Uytterhoeven wrote: > Hi Jacopo, > > CC linux-clk (yes I know this is about the legacy SH clock framework, but > the public API is/should be the same) > > On Thu, Jan 25, 2018 at 12:24 PM, Jacopo Mondi > wrote: > > When asking for a clk rate to be set, the sh core clock matches only > > exact rate values against the calculated frequency table entries. If the > > rate does not match exactly the test fails, and the whole frequency > > table is walked, resulting in selection of the last entry, corresponding to > > the lowest available clock rate. > > IIUIC, the code does not select the last entry, but returns an error code, > which is propagated all the way up? > > > Ie. when asking for a 10MHz clock rate on div6 clocks (ie. "video_clk" line), > > the calculated clock frequency 10088572 Hz gets ignored, and the clock is > > actually set to 5201920 Hz, which is the last available entry of the frequencies > > table. > > Perhaps 5201920 is just the default (or old value)? > > > Relax the clock frequency match test, allowing selection of clock rates > > immediately slower than the required one. > > > > Signed-off-by: Jacopo Mondi > > > > --- > > Hello renesas lists, > > > > I'm now working on handling frame rate for the ov7720 image sensor to have that > > driver accepted as part of v4l2. The sensor is installed on on Migo-R board. > > In order to properly calculate pixel clock and the framerate I noticed the > > clock signal fed to the sensor from the SH7722 chip was always the lowest > > available one. > > > > This patch fixes the issues and allows me to properly select which clock > > frequency supply to the sensor, which according to datasheet does not support > > input clock frequencies slower than 10MHz (but works anyhow). > > > > As all patches for SH architecture I wonder where they should be picked up from, > > as SH seems not maintained at the moment. > > > > Thanks > > j > > > > --- > > drivers/sh/clk/core.c | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c > > index 92863e3..d2cb94c 100644 > > --- a/drivers/sh/clk/core.c > > +++ b/drivers/sh/clk/core.c > > @@ -198,9 +198,12 @@ int clk_rate_table_find(struct clk *clk, > > { > > struct cpufreq_frequency_table *pos; > > > > - cpufreq_for_each_valid_entry(pos, freq_table) > > - if (pos->frequency == rate) > > - return pos - freq_table; > > + cpufreq_for_each_valid_entry(pos, freq_table) { > > + if (pos->frequency > rate) > > + continue; > > This assumes all frequency tables are sorted. > > Shouldn't you pick the closest frequency? > > However, that's what clk_rate_table_round() does, which is called from > sh_clk_div_round_rate(), and thus already used as .round_rate: > > static struct sh_clk_ops sh_clk_div_enable_clk_ops = { > .recalc = sh_clk_div_recalc, > .set_rate = sh_clk_div_set_rate, > .round_rate = sh_clk_div_round_rate, > .enable = sh_clk_div_enable, > .disable = sh_clk_div_disable, > }; Does this implies clock rates should be set using clk_round_rate() and not clk_set_rate() if I understand this right? > > (clk_rate_table_find() is called from sh_clk_div_set_rate()) > > Or are you supposed to ask for the exact clock rate? Where does the 10 MHz > come from? > From board initialization code, in order to provide a valid input clock to OV7720 sensor. The 10MHz seems like a workaround put in place to remove some image quality issues, according to the comment: https://elixir.free-electrons.com/linux/v4.15-rc9/source/arch/sh/boards/mach-migor/setup.c#L311 Thanks j > > + > > + return pos - freq_table; > > + } > > > > return -ENOENT; > > } > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds