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[209.132.180.67]) by mx.google.com with ESMTP id w86si4780512pfa.304.2018.01.25.07.39.42; Thu, 25 Jan 2018 07:39:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751223AbeAYPim convert rfc822-to-8bit (ORCPT + 99 others); Thu, 25 Jan 2018 10:38:42 -0500 Received: from hermes.aosc.io ([199.195.250.187]:51873 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750769AbeAYPik (ORCPT ); Thu, 25 Jan 2018 10:38:40 -0500 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 12FEC56507; Thu, 25 Jan 2018 15:38:36 +0000 (UTC) Date: Thu, 25 Jan 2018 23:38:04 +0800 In-Reply-To: <20180125153520.lxcfvh3yvi36uiux@flea.lan> References: <20180119231735.61504-1-icenowy@aosc.io> <20180122121435.bpayxk4uzfqbhqse@flea.lan> <14593819.uISRktVE4V@ice-x220i> <20180125153520.lxcfvh3yvi36uiux@flea.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Subject: Re: [RFC PATCH 0/9] initial support for "suniv" Allwinner new ARM9 SoC To: Maxime Ripard CC: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, Marc Zyngier , Linus Walleij , Daniel Lezcano , Russell King , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Chen-Yu Tsai , linux-clk@vger.kernel.org From: Icenowy Zheng Message-ID: <2A78FC75-61C0-4317-A7A1-6E1E42098C07@aosc.io> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 于 2018年1月25日 GMT+08:00 下午11:35:20, Maxime Ripard 写到: >Hi, > >On Wed, Jan 24, 2018 at 09:10:34PM +0800, Icenowy Zheng wrote: >> 在 2018年1月22日星期一 CST 下午8:14:35,Maxime Ripard 写道: >> > On Sat, Jan 20, 2018 at 07:17:26AM +0800, Icenowy Zheng wrote: >> > > This is the RFC initial patchset for the "new" Allwinner SUNIV >ARM9 SoC. >> > > >> > > The same die is packaged differently, come with different >co-packaged >> > > DRAM or shipped with different SDK; and then made many model >names: F23, >> > > F25, F1C100A, F1C100S, F1C200S, F1C500, F1C600, R6, etc. These >SoCs all >> > > share a common feature set and are packaged similarly (eLQFP128 >for SoCs >> > > without co-packaged DRAM, QFN88 for with DRAM). As their's no >> > > functionality hidden on the QFN88 models (except DRAM interface >not >> > > exported), it's not clever to differentiate them. So I will use >suniv as >> > > common name of all these SoCs. >> > >> > Where is that suniv prefix coming from? >> >> The BSP (Melis and Linux). (e.g. "libs/suniv" directory of the Melis >SDK and >> "arch/arm/boot/dts/sunivw1p1.dtsi" in the Linux SDK) > >Do you have a link to that BSP? I have it on the Baidu Pan. Is it acceptable? > >> > You should really answer two questions here: >> > - Are you able to predict whether you'll find an SoC part of that >> > family in the future that derives a bit and will need a >compatible >> > of its own? >> > - Are you able to predict which quirks we'll need along the way >to >> > support all the SoCs you've listed there? >> > >> > If you can't answer yes to both these questions, with a 100% >> > certainty, then you'll need a SoC name in the compatible. >> > >> > Which doesn't prevent you from sharing as much as possible the DT >like >> > we did between the A10s and the A13 for example. >> >> So the suniv-f1c100s.dtsi will still be kept empty and all >peripherals known >> should go through suniv.dtsi. > >Sorry if I wasn't really clear. You can totally keep the current DT >structure if that makes sense (and judging by what you're saying, it >does.), but the compatibles should have the SoC name in it. Okay. > >Maxime