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[209.132.180.67]) by mx.google.com with ESMTP id k10si1764570pgs.499.2018.01.25.08.37.56; Thu, 25 Jan 2018 08:38:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751228AbeAYQg6 (ORCPT + 99 others); Thu, 25 Jan 2018 11:36:58 -0500 Received: from mga05.intel.com ([192.55.52.43]:8757 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751086AbeAYQg5 (ORCPT ); Thu, 25 Jan 2018 11:36:57 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jan 2018 08:36:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,412,1511856000"; d="scan'208";a="13130332" Received: from marshy.an.intel.com ([10.122.105.159]) by fmsmga008.fm.intel.com with ESMTP; 25 Jan 2018 08:36:56 -0800 From: richard.gong@linux.intel.com To: arnd@arndb.de, gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, richard.gong@intel.com Subject: [PATCHv1] Add Intel Stratix10 service layer driver Date: Thu, 25 Jan 2018 10:39:03 -0600 Message-Id: <1516898344-20020-1-git-send-email-richard.gong@linux.intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Richard Gong Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware which does the FPGA configuration, QSPI, Crypto and warm reset. When the FPGA is configured from HPS, there needs to be a way for HPS to notify SDM the location and size of the configuration data. Then SDM will get the configuration data from that location and perform the FPGA configuration. To meet the whole system security needs and support virtual machine requesting communication with SDM, only the secure world of software (EL3, Exception Level 3) can interface with SDM. All software entities running on other exception levels must channel through the EL3 software whenever it needs service from SDM. Intel Stratix10 service layer driver is added to provide the service for FPGA configuration. Running at privileged exception level (EL1, Exception Level 1), Intel Stratix10 service layer driver interfaces with the service provider at EL1 (Intel Stratix10 FPGA Manager) and manages secure monitor call (SMC) to communicate with secure monitor software at secure monitor exception level (EL3). Later the Intel Stratix10 service layer driver will be extended to provide services for QSPI, Crypto and warm reset. Richard Gong (1): driver: misc: add Intel Stratix10 service layer driver drivers/misc/Kconfig | 3 +- drivers/misc/Makefile | 3 +- drivers/misc/intel-service/Kconfig | 9 + drivers/misc/intel-service/Makefile | 2 + drivers/misc/intel-service/intel_service.c | 703 +++++++++++++++++++++++++++++ include/linux/intel-service-client.h | 227 ++++++++++ include/linux/intel-service.h | 122 +++++ include/linux/intel-smc.h | 246 ++++++++++ 8 files changed, 1313 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/intel-service/Kconfig create mode 100644 drivers/misc/intel-service/Makefile create mode 100644 drivers/misc/intel-service/intel_service.c create mode 100644 include/linux/intel-service-client.h create mode 100644 include/linux/intel-service.h create mode 100644 include/linux/intel-smc.h -- 2.7.4