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[209.132.180.67]) by mx.google.com with ESMTP id u78si1771919pgb.481.2018.01.25.08.54.25; Thu, 25 Jan 2018 08:54:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751306AbeAYQx6 (ORCPT + 99 others); Thu, 25 Jan 2018 11:53:58 -0500 Received: from mail.linuxfoundation.org ([140.211.169.12]:44800 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbeAYQx5 (ORCPT ); Thu, 25 Jan 2018 11:53:57 -0500 Received: from localhost (unknown [37.171.117.151]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 533531050; Thu, 25 Jan 2018 16:53:55 +0000 (UTC) Date: Thu, 25 Jan 2018 17:53:52 +0100 From: Greg KH To: richard.gong@linux.intel.com Cc: arnd@arndb.de, linux-kernel@vger.kernel.org, richard.gong@intel.com Subject: Re: [PATCHv1] Add Intel Stratix10 service layer driver Message-ID: <20180125165352.GA21640@kroah.com> References: <1516898344-20020-1-git-send-email-richard.gong@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1516898344-20020-1-git-send-email-richard.gong@linux.intel.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 25, 2018 at 10:39:03AM -0600, richard.gong@linux.intel.com wrote: > From: Richard Gong > > Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard > processor system (HPS) and Secure Device Manager (SDM). SDM is the hardware > which does the FPGA configuration, QSPI, Crypto and warm reset. > > When the FPGA is configured from HPS, there needs to be a way for HPS to > notify SDM the location and size of the configuration data. Then SDM will > get the configuration data from that location and perform the FPGA configuration. > > To meet the whole system security needs and support virtual machine > requesting communication with SDM, only the secure world of software (EL3, > Exception Level 3) can interface with SDM. All software entities running > on other exception levels must channel through the EL3 software whenever it > needs service from SDM. > > Intel Stratix10 service layer driver is added to provide the service for > FPGA configuration. Running at privileged exception level (EL1, Exception > Level 1), Intel Stratix10 service layer driver interfaces with the service > provider at EL1 (Intel Stratix10 FPGA Manager) and manages secure monitor > call (SMC) to communicate with secure monitor software at secure monitor > exception level (EL3). > > Later the Intel Stratix10 service layer driver will be extended to provide > services for QSPI, Crypto and warm reset. > > Richard Gong (1): > driver: misc: add Intel Stratix10 service layer driver > > drivers/misc/Kconfig | 3 +- > drivers/misc/Makefile | 3 +- > drivers/misc/intel-service/Kconfig | 9 + > drivers/misc/intel-service/Makefile | 2 + > drivers/misc/intel-service/intel_service.c | 703 +++++++++++++++++++++++++++++ > include/linux/intel-service-client.h | 227 ++++++++++ > include/linux/intel-service.h | 122 +++++ > include/linux/intel-smc.h | 246 ++++++++++ Simple questions first: - why do you have 3 different .h files for a single .c file? - why do you have any public .h files for a single .c file? - use the correct SPDX markers for your file licenses, Intel legal knows all about this, please follow their rules. - why is this in a subdirectory for a single .c file? thanks, greg k-h