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Date:   Thu, 25 Jan 2018 19:11:10 +0200
From:   "Michael S. Tsirkin" <mst@redhat.com>
To:     Paolo Bonzini <pbonzini@redhat.com>
Cc:     Jason Wang <jasowang@redhat.com>,
        Radim =?utf-8?B?S3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        Liran Alon <liran.alon@oracle.com>, vkuznets@redhat.com,
        x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH] x86/kvm: disable fast MMIO when running nested
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On Thu, Jan 25, 2018 at 09:49:22AM -0500, Paolo Bonzini wrote:
> > > Michael and Jason, any progress on implementing a fast virtio mechanism
> > > that doesn't rely on undefined behavior?
> > >
> > > (Encode writing instruction length into last 4 bits of MMIO address,
> > >   side-channel say that accesses to the MMIO area always use certain
> > >   instruction length, use hypercall, ...)
> > >
> > > Thanks.
> > 
> > No progress from my side. But we can use PIO for virtio 1.0 and it's
> > faster than fast MMIO (qemu supports modern pio notification bar, we can
> > make it as default). It looks to me that neither encoding nor hypercall
> > will work for real hardware virtio device.
> 
> Encoding the instruction length would work, the h/w virtio devices would
> just ignore it.  But... it is really ugly.
> 
> Using PIO would be a small step backwards for PCIe.  As long as the device
> only needs *one* notification register (either MMIO or PIO) to initialize
> successfully, it's okay.  Then if there is no PIO space you'd just fall back
> to the slower MMIO notification.
> 
> Paolo

A bigger issue for PIO is it's causing exits for hw devices.


-- 
MST