Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Thu, 25 Jan 2018 22:37:30 +0100 (CET)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     Borislav Petkov <bp@alien8.de>
cc:     David Woodhouse <dwmw@amazon.co.uk>,
        Tom Lendacky <thomas.lendacky@amd.com>, arjan@linux.intel.com,
        karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org,
        tim.c.chen@linux.intel.com, peterz@infradead.org,
        pbonzini@redhat.com, ak@linux.intel.com,
        torvalds@linux-foundation.org, gregkh@linux-foundation.org,
        dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk,
        ashok.raj@intel.com, mingo@kernel.org
Subject: Re: [PATCH v5 3/7] x86/cpufeatures: Add AMD feature bits for
 Speculation Control
In-Reply-To: <20180125213048.yd5cloxh2ttggeas@pd.tnic>
Message-ID: <alpine.DEB.2.20.1801252235520.2203@nanos>
References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> <20180125213048.yd5cloxh2ttggeas@pd.tnic>
User-Agent: Alpine 2.20 (DEB 67 2015-01-07)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Thu, 25 Jan 2018, Borislav Petkov wrote:

> + Tom.
> 
> On Thu, Jan 25, 2018 at 04:14:11PM +0000, David Woodhouse wrote:
> > AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel.
> > See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com
> > 
> > Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
> > Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > ---
> >  arch/x86/include/asm/cpufeatures.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 0a51070..ae3212f 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -269,6 +269,9 @@
> >  #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
> >  #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
> >  #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
> > +#define X86_FEATURE_AMD_PRED_CMD	(13*32+12) /* Prediction Command MSR (AMD) */
> > +#define X86_FEATURE_AMD_SPEC_CTRL	(13*32+14) /* Speculation Control MSR only (AMD) */
> > +#define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */
> 
> So this leaf is AMD-specific so you can drop the AMD strings above.
> Also, let's simplify this as those flags appear in /proc/cpuinfo:
> 
> #define X86_FEATURE_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier: Prediction Command MSR */
> #define X86_FEATURE_IBRS		(13*32+14) /* Speculation Control MSR only */
> #define X86_FEATURE_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */
> 
> so that we have "ibpb", "ibrs" and "stibp" respectively.

That wont work as the intel bits are at a different leave and we cant
define the same thing twice....

Thanks,

	tglx