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[209.132.180.67]) by mx.google.com with ESMTP id y2si2048081pgo.193.2018.01.25.13.46.29; Thu, 25 Jan 2018 13:46:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=OQqdzj7t; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751353AbeAYVqF (ORCPT + 99 others); Thu, 25 Jan 2018 16:46:05 -0500 Received: from mail-ot0-f180.google.com ([74.125.82.180]:34335 "EHLO mail-ot0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751174AbeAYVqE (ORCPT ); Thu, 25 Jan 2018 16:46:04 -0500 Received: by mail-ot0-f180.google.com with SMTP id x15so8260161ote.1 for ; Thu, 25 Jan 2018 13:46:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=3YWi6YRvZq/jxJ/GdA4fGxTmXJIwDnujXFuK0uMiQa0=; b=OQqdzj7t7qNt4d7diwJWUz6LOTGXaCCqFo3t14X9nR0HWoY0dVO7hz+yhKtr+85zPD U208GBHJp4W9Hk6BXZ0oIP83y5O2eYRk/jIX73j2ORhhFos2NoE7ZcTndQemAiFm4Q+w hOmmEpbvgTtszviri8eLXGu1/AoWILgixcdqJv6j4nFqI1xH/WmVzJGQu5UnpOF9xB8S bnoMV5do2jQbYqbqX2hDt/LtA42af7e2XUC7VK0DJcI4kFG2884bxWEDMfFqLBYaSYSF HzaBshMrOQuLOe6cJG0nMxEnpn/A3XhqEAIlq/HCMlozmmWEHsBV9khFdHd9km8LQKUo IRKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=3YWi6YRvZq/jxJ/GdA4fGxTmXJIwDnujXFuK0uMiQa0=; b=QF2oQU0EQwhumabrnGBzAT8MJXkY9UkHmdtUu5+mUajeBFdd7TRYo0Al+BH2KhOq6r as+Lb3lxwamLJoYVunlHsvnMwKqjJJmC9E1bOMx8fBiR6XGAflvp5Q4vwHbSHAuP2+DC +kXD9aa2Z4uoT/x+XXTdS9wQ95MHOeErLis9zt0Q4XlLVDGbyz/b24eHXNbzgEAkX8OX skWZ4irRUo8pJfNHUnwvh3JhtqT6LV7PBNR6G9jqXtT0Ptydm97pB9FI32HiudckDJVd 0xivTgR4zoOXAVt87KYDG/Gm3VeS8mQmLH8uTBXY6QqG7C3Kl8ATqgYK2ufl6WqdF25o xi0A== X-Gm-Message-State: AKwxytdbhET4nxmZxA+P8bzE/7o0vxTM4FVDsb2qtzWgT57YhVwPVS6V 1w0qiBCSB7il1tG6r34qXsf9HNdIuO1CegGIjjlrKw== X-Received: by 10.157.54.226 with SMTP id s31mr12491074otd.280.1516916763763; Thu, 25 Jan 2018 13:46:03 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.24.23 with HTTP; Thu, 25 Jan 2018 13:46:03 -0800 (PST) In-Reply-To: References: <017877bf-5848-53c4-1f72-d630b3acaed4@ltec.ch> From: Bartosz Golaszewski Date: Thu, 25 Jan 2018 22:46:03 +0100 Message-ID: Subject: Re: nvmem: add driver for Microchip 24AA025E48 I2C eeprom / nodeID chip To: Felix Brack Cc: Andy Shevchenko , Srinivas Kandagatla , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-01-25 15:37 GMT+01:00 Felix Brack : > > On 24.01.2018 17:02, Bartosz Golaszewski wrote: >> 2018-01-24 16:18 GMT+01:00 Felix Brack : >>> >>> On 24.01.2018 16:08, Andy Shevchenko wrote: >>>> On Wed, Jan 24, 2018 at 4:23 PM, Felix Brack wrote: >>>>> Hello, >>>>> >>>>> About three years ago I wrote a driver for Microchip's 24AA025E48 I2C >>>>> eeprom/nodeID chip. At that time I placed the source files in >>>>> drivers/misc/eeprom. I never posted the code. >>>>> I now plan to rewrite the driver from scratch. Is it correct to place >>>>> the source code in drivers/nvmem and is there a special mailing list to >>>>> which the patch should be posted when ready? >>>>> >>>>> many thanks and kind regards, Felix >>>> >>>> Does the existing driver [1] work for you (if you add ID there)? >>>> >>>> [1]: at24 >>>> >>> Yes it does. Actually the driver I wrote 3 years ago is based on the >>> at24 driver. Lot's of code in my driver originates directly from the >>> at24 driver. >>> >>> -- >>> regards Felix >> >> Just from looking at the doc - it seems that it's a variant of >> 24mac402. You should be able to access the memory block by >> instantiating an 'atmel,24c02' device. As for the EUI-48 block - >> current at24 driver will not work as the MAC is located at a different >> offset in this chip. We need to figure out a portable way to specify >> the addresses of such special blocks (same with the serial number) in >> the at24 driver. >> >> Anyways - don't write your own driver for that, just make sure at24 works. >> > If no one offends against blowing up this driver by some more code, then > that's fine with me. What about a patch that does the following: > > 1. Extend the DT bindings by a new optional property block_offset > denoting where to start reading/writing from/to this device. > 2. Add a member block_offset to struct at24_platform_data{} to store > the device read/write offset returned from the DT (similar to the > already existing page_size member). > 3. Complement at24_get_pdata() to read block_offset from the DT and > store it. > 4. Make at24_eeprom_write_i2c() and at24_eeprom_read_serial() (and > eventually more?) respect the block_offset value. > These routines no longer exist, at24 uses regmap now. Please see current next or wait for 4.16-rc1. > Initializing the new block_offset member of struct at24_platform_data{} > to 0 should leave the code semantically unchanged. > > Once this patch is in place I could use the 24mac402 device type with > block_offset set to 0xfa (and read-only set to true) to read the EUI-48 > node address from Microchip's 24AA025E48. Probably the later addition of > a device named 24eui48 would also make sense (if not redundant ?). > > Any comments are very appreciated, Felix We should probably have a default value defined in chip data too, otherwise we'd break the existing models from atmel containing the EUI block (at24mac402/602) the offset of which is different than the one you're using. Best regards, Bartosz Golaszewski