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[209.132.180.67]) by mx.google.com with ESMTP id f11-v6si3348133plj.596.2018.01.25.23.40.17; Thu, 25 Jan 2018 23:40:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=aRDfIPe5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752126AbeAZHjd (ORCPT + 99 others); Fri, 26 Jan 2018 02:39:33 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:43950 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752058AbeAZHiq (ORCPT ); Fri, 26 Jan 2018 02:38:46 -0500 Received: by mail-pg0-f68.google.com with SMTP id n17so6749955pgf.10 for ; Thu, 25 Jan 2018 23:38:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qrqdTxU2Jm17iZTz1p39fDLLpaPbf8rpqrXTR3Katz8=; b=aRDfIPe5IgpTGL7ztJDUFAvNoduuWnYWtzswbiJ810fXu/mGAeZnAQCSTPI34hwIQ4 OZVRvdgS+BacsaH173tx9uDGWI2A/+x8t+J2EMEVrxvYSKH8fHx+Dw3kPYWqZuixMkR7 n1wN68ShEgo6acxzW/I+GVnu/wLU28TwShe1M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qrqdTxU2Jm17iZTz1p39fDLLpaPbf8rpqrXTR3Katz8=; b=uDvnV/SMVjwRaVjsHvLrTcC/UBkOZ9f6glC735VtFvM71puo4fqrNSed2UHVewlHhM 9gQuLcSqzgMvmMGWcwCkRU7SDh7nY9oj1/3HQ0INdyg5eqqShO76zsWPiKwMQvhLqRqn 3zp1LsoGf7LCddChnyWfI0O5ms7SwEXHtTDw4NnOKzE4NrgMLP8Xtq372uhuJmYriBzP brvMlWT0RjmFqW8tvhTb+INk9WwFGCgF3IKt7amkdq4id/eiN2or0LNUe/BCBX/viZPx AxNN4L4phpWBat2Wl6l1H+zwqAmgs565TCu61uBPtPWpvReUcnygnq7r3vYcns65Pfb1 CQ9Q== X-Gm-Message-State: AKwxyte89UTKop59qgdLIdUR/QdX3ovwVJCTGkFCd4drqyfrc+b0OeWM jlxr1uFkOupFjOdnT/lu2V/IzAYr4MY= X-Received: by 10.99.55.65 with SMTP id g1mr6052053pgn.284.1516952325442; Thu, 25 Jan 2018 23:38:45 -0800 (PST) Received: from exogeni.mtv.corp.google.com ([2620:0:1000:1600:211e:5908:95bc:4888]) by smtp.gmail.com with ESMTPSA id t22sm17856168pfi.118.2018.01.25.23.38.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 23:38:44 -0800 (PST) From: Derek Basehore To: linux-kernel@vger.kernel.org Cc: Soby.Mathew@arm.com, sudeep.holla@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, tglx@linutronix.de, briannorris@chromium.org, marc.zyngier@arm.com, Derek Basehore Subject: [PATCH v2 4/5] irqchip/gic-v3-its: add ability to resend MAPC on resume Date: Thu, 25 Jan 2018 23:38:34 -0800 Message-Id: <20180126073835.16575-5-dbasehore@chromium.org> X-Mailer: git-send-email 2.16.0.rc1.238.g530d649a79-goog In-Reply-To: <20180126073835.16575-1-dbasehore@chromium.org> References: <20180126073835.16575-1-dbasehore@chromium.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds functionality to resend the MAPC command to an ITS node on resume. If the ITS is powered down during suspend and the collections are not backed by memory, the ITS will lose that state. This just sets up the known state for the collections after the ITS is restored. This feature is enabled via Kconfig and the device tree. Signed-off-by: Derek Basehore --- arch/arm64/Kconfig | 10 ++++ drivers/irqchip/irq-gic-v3-its.c | 101 ++++++++++++++++++++++++--------------- 2 files changed, 73 insertions(+), 38 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 53612879fe56..f38f1a7b4266 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -571,6 +571,16 @@ config HISILICON_ERRATUM_161600802 If unsure, say Y. +config ARM_GIC500_COLLECTIONS_RESET + bool "GIC-500 Collections: Workaround for GIC-500 Collections on suspend reset" + default y + help + The GIC-500 can store Collections state internally for the ITS. If + the ITS is reset on suspend (ie from power getting disabled), the + collections need to be reconfigured on resume. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_E1041 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 4727b447610f..7633ea2b0a3c 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -48,6 +48,7 @@ #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) +#define ITS_FLAGS_WORKAROUND_GIC500_MAPC (1ULL << 4) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -1950,52 +1951,53 @@ static void its_cpu_init_lpis(void) dsb(sy); } -static void its_cpu_init_collection(void) +static void its_cpu_init_collection(struct its_node *its) { - struct its_node *its; - int cpu; - - spin_lock(&its_lock); - cpu = smp_processor_id(); - - list_for_each_entry(its, &its_nodes, entry) { - u64 target; + int cpu = smp_processor_id(); + u64 target; - /* avoid cross node collections and its mapping */ - if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { - struct device_node *cpu_node; + /* avoid cross node collections and its mapping */ + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { + struct device_node *cpu_node; - cpu_node = of_get_cpu_node(cpu, NULL); - if (its->numa_node != NUMA_NO_NODE && - its->numa_node != of_node_to_nid(cpu_node)) - continue; - } + cpu_node = of_get_cpu_node(cpu, NULL); + if (its->numa_node != NUMA_NO_NODE && + its->numa_node != of_node_to_nid(cpu_node)) + return; + } + /* + * We now have to bind each collection to its target + * redistributor. + */ + if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { /* - * We now have to bind each collection to its target + * This ITS wants the physical address of the * redistributor. */ - if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { - /* - * This ITS wants the physical address of the - * redistributor. - */ - target = gic_data_rdist()->phys_base; - } else { - /* - * This ITS wants a linear CPU number. - */ - target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); - target = GICR_TYPER_CPU_NUMBER(target) << 16; - } + target = gic_data_rdist()->phys_base; + } else { + /* This ITS wants a linear CPU number. */ + target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); + target = GICR_TYPER_CPU_NUMBER(target) << 16; + } - /* Perform collection mapping */ - its->collections[cpu].target_address = target; - its->collections[cpu].col_id = cpu; + /* Perform collection mapping */ + its->collections[cpu].target_address = target; + its->collections[cpu].col_id = cpu; - its_send_mapc(its, &its->collections[cpu], 1); - its_send_invall(its, &its->collections[cpu]); - } + its_send_mapc(its, &its->collections[cpu], 1); + its_send_invall(its, &its->collections[cpu]); +} + +static void its_cpu_init_collections(void) +{ + struct its_node *its; + + spin_lock(&its_lock); + + list_for_each_entry(its, &its_nodes, entry) + its_cpu_init_collection(its); spin_unlock(&its_lock); } @@ -2997,6 +2999,18 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) return true; } +static bool __maybe_unused its_enable_quirk_gic500_collections(void *data) +{ + struct its_node *its = data; + + if (fwnode_property_present(its->fwnode_handle, + "collections-reset-on-suspend")) { + its->flags |= ITS_FLAGS_WORKAROUND_GIC500_MAPC; + return true; + } + return false; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -3042,6 +3056,14 @@ static const struct gic_quirk its_quirks[] = { .mask = 0xffffffff, .init = its_enable_quirk_hip07_161600802, }, +#endif +#ifdef CONFIG_ARM_GIC500_COLLECTIONS_RESET + { + .desc = "ITS: GIC-500 Collections Reset on Resume", + .iidr = 0x00000000, + .mask = 0xff000000, + .init = its_enable_quirk_gic500_collections, + }, #endif { } @@ -3114,6 +3136,9 @@ void its_restore_enable(void) } writel_relaxed(ctx->ctlr, base + GITS_CTLR); } + + if (its->flags & ITS_FLAGS_WORKAROUND_GIC500_MAPC) + its_cpu_init_collection(its); } spin_unlock(&its_lock); } @@ -3380,7 +3405,7 @@ int its_cpu_init(void) return -ENXIO; } its_cpu_init_lpis(); - its_cpu_init_collection(); + its_cpu_init_collections(); } return 0; -- 2.16.0.rc1.238.g530d649a79-goog