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Message-ID: <1516969631.30244.215.camel@infradead.org>
Subject: Re: [PATCH v3 5/6] x86/pti: Do not enable PTI on processors which
 are not vulnerable to Meltdown
From:   David Woodhouse <dwmw2@infradead.org>
To:     Yves-Alexis Perez <corsac@debian.org>, arjan@linux.intel.com,
        tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org,
        linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com,
        bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com,
        ak@linux.intel.com, torvalds@linux-foundation.org,
        gregkh@linux-foundation.org, dave.hansen@intel.com,
        gnomes@lxorguk.ukuu.org.uk
In-Reply-To: <1516968886.19619.7.camel@debian.org>
References: <1516813025-10794-1-git-send-email-dwmw@amazon.co.uk>
         <1516813025-10794-6-git-send-email-dwmw@amazon.co.uk>
         <1516968886.19619.7.camel@debian.org>
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Date:   Fri, 26 Jan 2018 12:27:11 +0000
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On Fri, 2018-01-26 at 13:14 +0100, Yves-Alexis Perez wrote:
> On Wed, 2018-01-24 at 16:57 +0000, David Woodhouse wrote:
> > Some old Atoms, anything in family 5 or 4, and newer CPUs when they adv=
ertise
> > the IA32_ARCH_CAPABILITIES MSR and it has the RDCL_NO bit set, are not =
vulnerable.
> >=C2=A0
> > Roll the AMD exemption into the x86_match_cpu() table too.
> >=C2=A0
> > Based on suggestions from Dave Hansen and Alan Cox.
>=20
> Hi David,
>=20
> I know we'll still be able to manually enable PTI with a command line opt=
ion,
> but it's also a hardening feature which has the nice side effect of emula=
ting
> SMEP on CPU which don't support it (e.g the Atom boxes above).
>=20
> Couldn't we keep the =E2=80=9Cdefault on=E2=80=9D? Or maybe on boxes whic=
h also have CPID (in
> order to limit the performance cost)?

Strictly speaking, "don't enable PTI" is a side-effect of my patch, not
directly what it does.

All this patch does is *correctly* refrain from setting
X86_BUG_CPU_MELTDOWN on CPUs which don't suffer that bug.

It's the logic in=C2=A0arch/x86/mm/pti.c which enables PTI by default only
for CPUs with the the bug.

As for whether PCID reduces the performance hit sufficiently to make it wor=
thwhile, "just" to emulate SMEP, I'm not sure. But I am sure it's someone e=
lse's problem for today except as a cosmetic comment on the headline of my =
patch :)

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