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[209.132.180.67]) by mx.google.com with ESMTP id k83si6380125pfa.246.2018.01.26.04.40.20; Fri, 26 Jan 2018 04:40:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=SwhNBqK8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752078AbeAZMju (ORCPT + 99 others); Fri, 26 Jan 2018 07:39:50 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:32810 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751406AbeAZMjs (ORCPT ); Fri, 26 Jan 2018 07:39:48 -0500 Received: by mail-qt0-f195.google.com with SMTP id d8so901141qtm.0; Fri, 26 Jan 2018 04:39:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Waekfd75OyQakj1m03QBwxfh1BDNjHtRYFjtZ/5utkk=; b=SwhNBqK8UtHm3eqhwU5rLQUsygW96NTN6Zmgb9taHX3JELPhjPEvDbdEIWrAmX662M 86shyWG8xCZ9/+9mGaleiY8XUQewYY4yoQtOwqz0xRMn2JSdpYhzK3r7wQ4l0kWDM18e nrj9WKSX8tbhVlrrhdFL08pPqqZHO9Z/MfF85z+yRhlYq8fy4cwg5Um0UaCxU/St45bz VGxpXvEG/xy7ml5WWWxXFpP5aSjt6U5QWwON0LXgmWZ3785xq0QtdTK+Qfcz7fgQyTVN BKhJAdn1vBjfHplfYDwaWVli1eceXc/eBlYpwwcaZ3AiORciAij0pbLcyKXn5icEIw6T K6gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Waekfd75OyQakj1m03QBwxfh1BDNjHtRYFjtZ/5utkk=; b=AWfF3JdlptMZQjplGcVv3S0VXSfjYXlr3kveikGRiinYpXwhYb9NfOaKpx6qC3mDyc w6++nNbeabTOzsoHJHHAW64Nt1YW7PfS7xyDOw3WV6952gDQDcZmfOX/EibmBB6zhz6/ ImBCPzPDYri0UqGlzEgV3dgQxQJow0uxD5rK/5mMD9+4zhpi8td5yaJwUpH7d90vSGX6 S6ZG7oTUH04okmMIM/9F40AvbW6fDvIprs6qTILfNuf6y0mG0jQfGCV/KZpSZIj6RUsz rDI3LR3W1v926eCAOcrNeY5hJkMqjnV9xBx1SQBSdTXhdQsRAUlYpY3ANxhIzPqIEaXD LGeA== X-Gm-Message-State: AKwxytcXhkl/q3+tbBtPXx+by1eEdK35ZkffpnUesrb6OSkZtA8gj1US kPy7sWSiRnKNI3I2/OTOO7jVsy3TDGRJQwHiIP8= X-Received: by 10.55.96.4 with SMTP id u4mr20293258qkb.323.1516970387898; Fri, 26 Jan 2018 04:39:47 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.175.35 with HTTP; Fri, 26 Jan 2018 04:39:47 -0800 (PST) In-Reply-To: <1516352307-20123-7-git-send-email-rajneesh.bhardwaj@intel.com> References: <1516352307-20123-1-git-send-email-rajneesh.bhardwaj@intel.com> <1516352307-20123-7-git-send-email-rajneesh.bhardwaj@intel.com> From: Andy Shevchenko Date: Fri, 26 Jan 2018 14:39:47 +0200 Message-ID: Subject: Re: [Patch v1 6/8] x86/cpu: Add Cannonlake to Intel family To: Rajneesh Bhardwaj Cc: Platform Driver , Darren Hart , Andy Shevchenko , Linux Kernel Mailing List , Vishwanath Somayaji , Srinivas Pandruvada , Dave Hansen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj wrote: > Add CPUID of Cannonlake (CNL) processors to Intel family list. > > Cc: Dave Hansen > Cc: Thomas Gleixner > cc: Ingo Molnar > Cc: "H. Peter Anvin" > Cc: x86@kernel.org Thomas, can you Ack this patch? > Suggested-by: Tony Luck > Signed-off-by: Megha Dey > Signed-off-by: Rajneesh Bhardwaj > --- > arch/x86/include/asm/intel-family.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h > index 35a6bc4da8ad..cf090e584202 100644 > --- a/arch/x86/include/asm/intel-family.h > +++ b/arch/x86/include/asm/intel-family.h > @@ -10,6 +10,10 @@ > * > * Things ending in "2" are usually because we have no better > * name for them. There's no processor called "SILVERMONT2". > + * > + * While adding a new CPUID for a new microarchitecture, add a new > + * group to keep logically sorted out in chronological order. Within > + * that group keep the CPUID for the variants sorted by model number. > */ > > #define INTEL_FAM6_CORE_YONAH 0x0E > @@ -49,6 +53,8 @@ > #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E > #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E > > +#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66 > + > /* "Small Core" Processors (Atom) */ > > #define INTEL_FAM6_ATOM_PINEVIEW 0x1C > -- > 2.7.4 > -- With Best Regards, Andy Shevchenko