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Date:   Fri, 26 Jan 2018 19:41:39 +0100
From:   Borislav Petkov <bp@alien8.de>
To:     x86-ml <x86@kernel.org>
Cc:     linux-tip-commits@vger.kernel.org, hpa@zytor.com,
        gregkh@linuxfoundation.org, tglx@linutronix.de, dwmw@amazon.co.uk,
        thomas.lendacky@amd.com, linux-kernel@vger.kernel.org,
        mingo@kernel.org
Subject: [PATCH] x86/cpufeatures: Cleanup AMD speculation feature bits
Message-ID: <20180126184139.rcfbtk7dvj7kmyfn@pd.tnic>
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 <tip-5d10cbc91d9eb5537998b65608441b592eec65e7@git.kernel.org>
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On Fri, Jan 26, 2018 at 07:00:30AM -0800, tip-bot for David Woodhouse wrote:
> +#define X86_FEATURE_AMD_PRED_CMD	(13*32+12) /* Prediction Command MSR (AMD) */
> +#define X86_FEATURE_AMD_SPEC_CTRL	(13*32+14) /* Speculation Control MSR only (AMD) */
> +#define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */

Let's clean those up before it hits upstream.

Tom, scream if something's still wrong.

Thx.

---
From 41fa030b09992b097c6b57d69eebad4f07e228c4 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Fri, 26 Jan 2018 19:07:39 +0100
Subject: [PATCH] x86/cpufeatures: Cleanup AMD speculation feature bits

X86_FEATURE_AMD_PRED_CMD -> X86_FEATURE_AMD_IBPB

That is the preferred name. Also, hide it in /proc/cpuinfo as we're
setting a vendor-agnostic X86_FEATURE_IBPB one.

X86_FEATURE_AMD_SPEC_CTRL -> X86_FEATURE_IBRS

On AMD that's only the IBRS control bit.

Also, have X86_FEATURE_AMD_STIBP appear as "stibp" only in
/proc/cpuinfo, as Intel's feature does.

Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/include/asm/cpufeatures.h | 6 +++---
 arch/x86/kernel/cpu/bugs.c         | 2 +-
 arch/x86/kernel/cpu/intel.c        | 8 ++++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 40f92eff09df..6c6d862d66a1 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -272,9 +272,9 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
-#define X86_FEATURE_AMD_PRED_CMD	(13*32+12) /* Prediction Command MSR (AMD) */
-#define X86_FEATURE_AMD_SPEC_CTRL	(13*32+14) /* Speculation Control MSR only (AMD) */
-#define X86_FEATURE_AMD_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */
+#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier MSR */
+#define X86_FEATURE_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */
+#define X86_FEATURE_AMD_STIBP		(13*32+15) /* "stibp" Single Thread Indirect Branch Predictors */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c988a8acb0d5..be068aea6bda 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -266,7 +266,7 @@ static void __init spectre_v2_select_mitigation(void)
 
 	/* Initialize Indirect Branch Prediction Barrier if supported */
 	if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) ||
-	    boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) {
+	    boot_cpu_has(X86_FEATURE_AMD_IBPB)) {
 		setup_force_cpu_cap(X86_FEATURE_IBPB);
 		pr_info("Enabling Indirect Branch Prediction Barrier\n");
 	}
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7a3d216875fc..30d13afe726b 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -177,14 +177,14 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
 	if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
 	     cpu_has(c, X86_FEATURE_STIBP) ||
-	     cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) ||
-	     cpu_has(c, X86_FEATURE_AMD_PRED_CMD) ||
+	     cpu_has(c, X86_FEATURE_IBRS) ||
+	     cpu_has(c, X86_FEATURE_AMD_IBPB) ||
 	     cpu_has(c, X86_FEATURE_AMD_STIBP)) && bad_spectre_microcode(c)) {
 		pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL\n");
 		clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL);
 		clear_cpu_cap(c, X86_FEATURE_STIBP);
-		clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL);
-		clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD);
+		clear_cpu_cap(c, X86_FEATURE_IBRS);
+		clear_cpu_cap(c, X86_FEATURE_AMD_IBPB);
 		clear_cpu_cap(c, X86_FEATURE_AMD_STIBP);
 	}
 
-- 
2.13.0

-- 
Regards/Gruss,
    Boris.

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