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[209.132.180.67]) by mx.google.com with ESMTP id d65si3523420pga.399.2018.01.26.13.53.57; Fri, 26 Jan 2018 13:54:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752000AbeAZVwY (ORCPT + 99 others); Fri, 26 Jan 2018 16:52:24 -0500 Received: from mail.skyhub.de ([5.9.137.197]:50938 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751613AbeAZVwX (ORCPT ); Fri, 26 Jan 2018 16:52:23 -0500 X-Virus-Scanned: Nedap ESD1 at mail.skyhub.de Received: from mail.skyhub.de ([127.0.0.1]) by localhost (blast.alien8.de [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id bY3M33VCO0gb; Fri, 26 Jan 2018 22:52:22 +0100 (CET) Received: from pd.tnic (p200300EC2BCF3A0024194793E6CFFC7A.dip0.t-ipconnect.de [IPv6:2003:ec:2bcf:3a00:2419:4793:e6cf:fc7a]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id E7B281EC034B; Fri, 26 Jan 2018 22:52:21 +0100 (CET) Date: Fri, 26 Jan 2018 22:52:09 +0100 From: Borislav Petkov To: Tom Lendacky Cc: David Woodhouse , x86-ml , linux-tip-commits@vger.kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, mingo@kernel.org Subject: Re: [PATCH] x86/cpufeatures: Cleanup AMD speculation feature bits Message-ID: <20180126215209.vqdxh5p672tcdst6@pd.tnic> References: <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> <20180126184139.rcfbtk7dvj7kmyfn@pd.tnic> <1516992318.30244.271.camel@infradead.org> <20180126184915.ioqewp56orj2qhrt@pd.tnic> <7094ed9b-40f7-ba2b-55a6-cc5ab0b06bb9@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <7094ed9b-40f7-ba2b-55a6-cc5ab0b06bb9@amd.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 26, 2018 at 03:06:20PM -0600, Tom Lendacky wrote: > So I like the idea of AMD_IBRS/AMD_IBPB/AMD_STIBP and then use the magic > quotes as appropriate. We could probably use the magic quotes on > AMD_STIBP and set X86_FEATURE_STIBP when we see X86_FEATURE_AMD_STIBP. Like this? We set the respective Intel features when we detect the AMD ones so that we get correct /proc/cpuinfo strings. The respective AMD ones are not shown. --- diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 40f92eff09df..73080d5a5696 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -272,9 +272,9 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ -#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ -#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ -#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ +#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier MSR */ +#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Speculation Control MSR only */ +#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index ea831c858195..14c8a7869450 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -872,6 +872,12 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ if (!cpu_has(c, X86_FEATURE_XENPV)) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); + + if (cpu_has(c, X86_FEATURE_AMD_IBRS)) + set_cpu_cap(c, X86_FEATURE_IBRS); + + if (cpu_has(c, X86_FEATURE_AMD_STIBP)) + set_cpu_cap(c, X86_FEATURE_STIBP); } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index c988a8acb0d5..be068aea6bda 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -266,7 +266,7 @@ static void __init spectre_v2_select_mitigation(void) /* Initialize Indirect Branch Prediction Barrier if supported */ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) || - boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) { + boot_cpu_has(X86_FEATURE_AMD_IBPB)) { setup_force_cpu_cap(X86_FEATURE_IBPB); pr_info("Enabling Indirect Branch Prediction Barrier\n"); } diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 7a3d216875fc..571249b8bc00 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -177,14 +177,14 @@ static void early_init_intel(struct cpuinfo_x86 *c) if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || cpu_has(c, X86_FEATURE_STIBP) || - cpu_has(c, X86_FEATURE_AMD_SPEC_CTRL) || - cpu_has(c, X86_FEATURE_AMD_PRED_CMD) || + cpu_has(c, X86_FEATURE_AMD_IBRS) || + cpu_has(c, X86_FEATURE_AMD_IBPB) || cpu_has(c, X86_FEATURE_AMD_STIBP)) && bad_spectre_microcode(c)) { pr_warn("Intel Spectre v2 broken microcode detected; disabling SPEC_CTRL\n"); clear_cpu_cap(c, X86_FEATURE_SPEC_CTRL); clear_cpu_cap(c, X86_FEATURE_STIBP); - clear_cpu_cap(c, X86_FEATURE_AMD_SPEC_CTRL); - clear_cpu_cap(c, X86_FEATURE_AMD_PRED_CMD); + clear_cpu_cap(c, X86_FEATURE_AMD_IBRS); + clear_cpu_cap(c, X86_FEATURE_AMD_IBPB); clear_cpu_cap(c, X86_FEATURE_AMD_STIBP); } -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.