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[209.132.180.67]) by mx.google.com with ESMTP id y6-v6si5798390plt.467.2018.01.27.12.38.09; Sat, 27 Jan 2018 12:38:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=r2nTJcPe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752687AbeA0Uhf (ORCPT + 99 others); Sat, 27 Jan 2018 15:37:35 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:44728 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751406AbeA0Uhd (ORCPT ); Sat, 27 Jan 2018 15:37:33 -0500 Received: by mail-lf0-f66.google.com with SMTP id v188so4711261lfa.11; Sat, 27 Jan 2018 12:37:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=ZY0PrWSO1Me4I2x8ySP5QKKuudfFTD4nX/VJMil060s=; b=r2nTJcPeDvwbUv9hXVX6pp2kOYH+RUJj+3mjwyyIvFJslMFnw3fN1uBMnmJX6JztDx cNCQAuYp2qbbBPorXt4fd/fwPKtcWNnVDSKLt8aeCyJgbHNAzxODcQvW13gbV6m8ePPq K65MlzhSdsR9pN3sfe91HajAJraTj7G+GT2myxe/ojcWbt0/JIabQEsmR6mdotGjEGXX p3CQoJrha4UIPuEwUZ0Y3XuK6aUGMExASgJBCC1+JJgWzyaOV0d3n9uif3raSMeDZ7ms mNDHQ5pb5E09dhxvmJC7Af1ncndhjzk3KspHpYYHniGD+sbmat0SwXY/uRONz0v2xkJi TizA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=ZY0PrWSO1Me4I2x8ySP5QKKuudfFTD4nX/VJMil060s=; b=lHtxJ9R3MJbBKsfyh+QoEN+IXUoelEhHA0EmZTqI9lc9eFxPInY0vAkLsV8HdOGGVs LpHpojJ90ADTs510QQGesHfe+0T18HvnQBMYQUUqCDikjqotKY56EhTj12CaIA4SoApF NgZB+0iw/h0QUGMQM+31Q6xGNmVcDqlC3EQS4OALwuvZkxbh6UF+CPOqpRvR+Y7BVvIb 5wUVlPyQHPd/L8NCl/ruZhJ2ClbqDxvODilDm/kYzQUTAi3XJYEkU5ydLCsAcUqulCUa XGWg06zKVQ7nY4YDOF5TPZrljMZhFihwtfiu8mJrmPEDJCA3u6a9vPbkhtIvKHQb68et DlUw== X-Gm-Message-State: AKwxytdZ3aHY+qrYw0YzStAzX5+1HmYm+u9dFrd9ZVClHX4AJJ94H5kL EIrQ1RTGmY5gcxQJxNCfs+7R3chDYcygz6Tt4uM= X-Received: by 10.25.83.4 with SMTP id h4mr10936702lfb.121.1517085451988; Sat, 27 Jan 2018 12:37:31 -0800 (PST) MIME-Version: 1.0 Received: by 10.46.64.214 with HTTP; Sat, 27 Jan 2018 12:37:11 -0800 (PST) In-Reply-To: <20180127153733.7ziaq6frli3jemc7@pengutronix.de> References: <20180127000752.2879-1-benoit.thebaudeau.dev@gmail.com> <20180127153733.7ziaq6frli3jemc7@pengutronix.de> From: =?UTF-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Sat, 27 Jan 2018 21:37:11 +0100 Message-ID: Subject: Re: [PATCH] ARM: dts: imx25-pinfunc: Always set SION for SD CMD To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: linux-kernel , devicetree@vger.kernel.org, linux-arm-kernel , Russell King , Mark Rutland , Rob Herring , Fabio Estevam , Sascha Hauer , Shawn Guo , Michael Nazzareno Trimarchi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jan 27, 2018 at 4:37 PM, Uwe Kleine-K=C3=B6nig wrote: > On Sat, Jan 27, 2018 at 01:07:52AM +0100, Beno=C3=AEt Th=C3=A9baudeau wro= te: >> The eSDHC does not work properly if the SION bit is not set for the >> bidirectional CMD signal, whatever the eSDHC instance and the selected >> pad. Therefore, setting SION is mandatory for all eSDHC CMD ports. Do >> this for MX25_PAD_*__SD*_CMD in imx25-pinfunc.h in order to enforce this >> behavior for all boards. >> >> This had already been done for eSDHC1, but not for eSDHC2. Also, define >> MX25_PAD_FEC_MDC__SDHC2_CMD so that all the possible cases are covered >> from now on. > > There is an inconsistency in the naming. The eSDHC1 CMD constants are > named: > > MX25_PAD_SD1_CMD__SD1_CMD > > The reference calls this: > > CMD of instance: esdhc1. > > The register name is correct though. Not sure it's worth to fix this to > use consistent naming (which would result in: > > MX25_PAD_SD1_CMD__ESDHC1_CMD > > which looks ugly, too). Indeed. I had also noticed this. I can send a patch to apply before this one. But that would break the out-of-tree DT files using these definitions. Would that be OK? >> Signed-off-by: Beno=C3=AEt Th=C3=A9baudeau >> --- >> arch/arm/boot/dts/imx25-pinfunc.h | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25= -pinfunc.h >> index 6c63dca1b9b8..6cc71f7e1baa 100644 >> --- a/arch/arm/boot/dts/imx25-pinfunc.h >> +++ b/arch/arm/boot/dts/imx25-pinfunc.h >> @@ -236,7 +236,8 @@ >> #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x0= 00 >> #define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 = 0x02 0x000 >> #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x0= 00 >> -#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 = 0x06 0x000 >> +/* The eSDHC cannot work if SION is not set for the bidirectional CMD s= ignal. */ > > Maybe reference the more verbose comment for MX25_PAD_SD1_CMD__SD1_CMD > here? Good idea. That would avoid repeating the same thing everywhere while giving a pointer to more details. >> +#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 = 0x16 0x000 >> >> #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x0= 00 >> #define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 = 0x02 0x000 >> @@ -316,7 +317,8 @@ >> #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x0= 00 >> >> #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 = 0x00 0x000 >> -#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x0= 01 >> +/* The eSDHC cannot work if SION is not set for the bidirectional CMD s= ignal. */ >> +#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x0= 01 >> #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x0= 00 >> #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x0= 00 >> >> @@ -496,6 +498,8 @@ >> #define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x05 0x0= 00 >> >> #define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x00 0x0= 00 >> +/* The eSDHC cannot work if SION is not set for the bidirectional CMD s= ignal. */ >> +#define MX25_PAD_FEC_MDC__SDHC2_CMD 0x1c8 0x3c0 0x4e0 0x11 0x0= 02 >> #define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x02 0x0= 01 >> #define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x05 0x0= 00 > > I double checked the numbers, and these seem all to be correct. Thanks for your review. Best regards, Beno=C3=AEt