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[209.132.180.67]) by mx.google.com with ESMTP id i3-v6si9130245plt.369.2018.01.29.02.48.13; Mon, 29 Jan 2018 02:48:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f9uyE3Db; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751740AbeA2KrK (ORCPT + 99 others); Mon, 29 Jan 2018 05:47:10 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:34701 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751626AbeA2KrH (ORCPT ); Mon, 29 Jan 2018 05:47:07 -0500 Received: by mail-qt0-f195.google.com with SMTP id a27so12085260qtd.1 for ; Mon, 29 Jan 2018 02:47:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Z7a60yKliKnWDW/u0u0Ya1KwxCj9l4CCb6BaTIGJMbo=; b=f9uyE3DbCv1k9Wh5P7Q/2NrZVzf+9GpBuGU7W7xunfMGGPnnt3g8nvxwOlDtYL+p9S mc+1aUkHmsM/xCr9AcEu4Mau5Xgidp+SnqLN0V2XmBhm7Vu5ngGFnYKFyFczSrYCnxr0 DnJ1znHNVP6Lq7rwxo/bHkksbPs1Iwj2BT23Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Z7a60yKliKnWDW/u0u0Ya1KwxCj9l4CCb6BaTIGJMbo=; b=F58Ek979qQyfNi1Oc/+Xe0TlTZ0nzQnta017U+lBcwUiiEQH+gxYbi1r/zJRHcAW9d VzrteUs54NbLDS3hVnRCysDkuYo3nQ4ic6lLw7bGJTlBgHxQxpzRGh18sVhhvWkHqGE7 J4getzcP2XPsD5A8ZVBByn4WCpuOgxUVZjqqGUsH4mvw1zHpfJ2h++2tL8QZjKYXruvZ IXxSLkiBBufr/I5MgXgowxd8EypcSYdCXzG+vyAWBoUHU4IqEgrI2OsMnBrRPQDnqv3I Z/KGwiR5Mz5qCkS7kuhMjVUXQMVP1/bryy9eD/AT7E91FX05fwX9QeInhIAx0Ii3QY2/ 6IWQ== X-Gm-Message-State: AKwxyteucHfid7Mv5Rbl5uMHk7u0famIpzpVeICuAYIXGIFd1sjKTFG/ FuxcMYQuDPBBGlih7MSwmyjCS6Q9+0BwTI0IpCkB7Q== X-Received: by 10.200.3.41 with SMTP id q41mr37668134qtg.173.1517222825867; Mon, 29 Jan 2018 02:47:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.140.82.178 with HTTP; Mon, 29 Jan 2018 02:47:05 -0800 (PST) In-Reply-To: <1617432.LU6HsMfOQM@avalon> References: <20180125160101.9102-1-philippe.cornu@st.com> <1617432.LU6HsMfOQM@avalon> From: Benjamin Gaignard Date: Mon, 29 Jan 2018 11:47:05 +0100 Message-ID: Subject: Re: [PATCH] drm/stm: ltdc: use crtc_mode_fixup to update adjusted_mode clock To: Laurent Pinchart Cc: Philippe Cornu , Yannick Fertre , Vincent Abriou , David Airlie , dri-devel@lists.freedesktop.org, Linux Kernel Mailing List , Archit Taneja , Andrzej Hajda , Fabien Dessenne , Mickael Reulier , Ludovic Barre , Alexandre Torgue , Maxime Coquelin Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2018-01-29 11:43 GMT+01:00 Laurent Pinchart : > Hi Philippe, > > On Thursday, 25 January 2018 18:01:01 EET Philippe Cornu wrote: >> There is a difference between the panel/bridge requested pixel clock >> value and the real one due to the hw platform clock preciseness (pll, >> dividers...). This patch updates the adjusted_mode clock value with >> the real hw clock value so then attached encoder & connector can use >> it for precise timing computations. >> >> Signed-off-by: Philippe Cornu >> --- >> drivers/gpu/drm/stm/ltdc.c | 35 +++++++++++++++++++++++++---------- >> 1 file changed, 25 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c >> index b48589343ae1..90b3de516c91 100644 >> --- a/drivers/gpu/drm/stm/ltdc.c >> +++ b/drivers/gpu/drm/stm/ltdc.c >> @@ -428,12 +428,35 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc >> *crtc, reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); >> } >> >> +static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, >> + const struct drm_display_mode *mode, >> + struct drm_display_mode *adjusted_mode) >> +{ >> + struct ltdc_device *ldev = crtc_to_ltdc(crtc); >> + int rate = mode->clock * 1000; >> + >> + /* >> + * TODO clk_round_rate() does not work yet. When ready, it can >> + * be used instead of clk_set_rate() then clk_get_rate(). >> + */ > > Why does it fail ? Is it due to the STM clock source implementation ? This > looks like a big hack, I'd rather see clk_round_rate() being fixed. We have log the point and we will investigate it asap. Regards, Benjamin > >> + clk_disable(ldev->pixel_clk); >> + if (clk_set_rate(ldev->pixel_clk, rate) < 0) { >> + DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); >> + return false; >> + } >> + clk_enable(ldev->pixel_clk); >> + >> + adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; >> + >> + return true; >> +} >> + >> static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) >> { >> struct ltdc_device *ldev = crtc_to_ltdc(crtc); >> struct drm_display_mode *mode = &crtc->state->adjusted_mode; >> struct videomode vm; >> - int rate = mode->clock * 1000; >> u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; >> u32 total_width, total_height; >> u32 val; >> @@ -456,15 +479,6 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc >> *crtc) total_width = accum_act_w + vm.hfront_porch; >> total_height = accum_act_h + vm.vfront_porch; >> >> - clk_disable(ldev->pixel_clk); >> - >> - if (clk_set_rate(ldev->pixel_clk, rate) < 0) { >> - DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); >> - return; >> - } >> - >> - clk_enable(ldev->pixel_clk); >> - >> /* Configures the HS, VS, DE and PC polarities. Default Active Low */ >> val = 0; >> >> @@ -528,6 +542,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc >> *crtc, } >> >> static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { >> + .mode_fixup = ltdc_crtc_mode_fixup, >> .mode_set_nofb = ltdc_crtc_mode_set_nofb, >> .atomic_flush = ltdc_crtc_atomic_flush, >> .atomic_enable = ltdc_crtc_atomic_enable, > > -- > Regards, > > Laurent Pinchart >