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[87.143.4.210]) by smtp.gmail.com with ESMTPSA id z22sm2465385wrc.3.2018.01.29.07.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 29 Jan 2018 07:58:18 -0800 (PST) From: Philipp Rossak To: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, sean@mess.org, p.zabel@pengutronix.de, andi.shyti@samsung.com Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v4 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T Date: Mon, 29 Jan 2018 16:58:07 +0100 Message-Id: <20180129155810.7867-4-embed3d@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180129155810.7867-1-embed3d@gmail.com> References: <20180129155810.7867-1-embed3d@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CIR Pin of the A83T is located at PL12. Signed-off-by: Philipp Rossak --- arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index de5119a2a91c..06e96db7c41a 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -617,6 +617,11 @@ interrupt-controller; #interrupt-cells = <3>; + cir_pins: cir-pins@0 { + pins = "PL12"; + function = "s_cir_rx"; + }; + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; -- 2.11.0