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[209.132.180.67]) by mx.google.com with ESMTP id n3-v6si768316plp.487.2018.01.29.17.03.47; Mon, 29 Jan 2018 17:04:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=O8erSgW+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752332AbeA3BDT (ORCPT + 99 others); Mon, 29 Jan 2018 20:03:19 -0500 Received: from mail-ua0-f195.google.com ([209.85.217.195]:37539 "EHLO mail-ua0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751417AbeA3BDR (ORCPT ); Mon, 29 Jan 2018 20:03:17 -0500 Received: by mail-ua0-f195.google.com with SMTP id q8so6010888uae.4 for ; Mon, 29 Jan 2018 17:03:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=faCOieWVqAByuaJy1+9E4RIKvCmUU1Hv8OcCrBuGKRk=; b=O8erSgW+fHl50BlszgP3/0fPibqFkXKWur7Btfjo2y6sfrH6HnlBvA6Sf5oGEIMF9b VQGOEr4WByFrtsm/8sF5sgL3R/EYXl3zQl0Y5Gh4XvyzgMrJc34EJnSFar9/EeDKZMWg uWu7Tag2ix4CHnNZXoYtj0bGh8F56oOK1K8iXi2xho3CbMxCgmNcDIX0NmcJcD1dy1pa dUNVoJhWYdsMeDeeNX2NjN4O9BARK+7BEtRYHtAcNSGMxGs+rs10oaZgSzUo7JoHfjaD L+cSw+R8inHjY01N9GS7NkuKlUabT3RaY0rLCK8Ojs/G3whCNEB0A+0P9Hk/+xD5KAQg ki4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=faCOieWVqAByuaJy1+9E4RIKvCmUU1Hv8OcCrBuGKRk=; b=uHENfoCHneW9jFu2F9jUPLTYRKP1qCnqCE68QdTY3BWHxyi2faYfd5Jh6aX5RZOvMN /N2PujWU92eSwHZLscF47esehQG8zIp0OCTwc/AHLnVyzlYqHAVwvieYDygTNih9Gd7G 7W/wH5b++/r+WdixQWlJd84n8IvXPfi43+Zzw5gDb4HKI3EkIpV0mbemKpDNbbYrMkdm z1EyFonnz6pA6E5NbICS+uf3hfRyygKkJ6hTTpMNoMT0yKfdgoyeXIqdn/JqU2fdxLk4 Cg02gk6irrNMb6qYRDMq7XPxIpjTU4/9eQpdf/rUl86wv0I2WWn6fGcHP7AyzCj8CmVV dZ0Q== X-Gm-Message-State: AKwxytfxwpCoBK259oD2Uk4VbrREb5yls9UXzgbWwKBD1Mqmmv54R6y9 /L80LnyYV1+aEmWnY16kDQYht7oDYfnYx7oju2MWJA== X-Received: by 10.159.51.74 with SMTP id a10mr20559074uac.102.1517274195657; Mon, 29 Jan 2018 17:03:15 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.85.216 with HTTP; Mon, 29 Jan 2018 17:03:14 -0800 (PST) In-Reply-To: References: <1516476182-5153-6-git-send-email-karahmed@amazon.de> <20180129201404.GA1588@localhost.localdomain> <1517257022.18619.30.camel@infradead.org> <20180129204256.GV25150@localhost.localdomain> <31415b7f-9c76-c102-86cd-6bf4e23e3aee@linux.intel.com> <1517259759.18619.38.camel@infradead.org> From: Jim Mattson Date: Mon, 29 Jan 2018 17:03:14 -0800 Message-ID: Subject: Re: [RFC,05/10] x86/speculation: Add basic IBRS support infrastructure To: Linus Torvalds Cc: David Woodhouse , Arjan van de Ven , Eduardo Habkost , KarimAllah Ahmed , Linux Kernel Mailing List , Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Masami Hiramatsu , Paolo Bonzini , Peter Zijlstra , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Thomas Gleixner , Tim Chen , Tom Lendacky , KVM list , "the arch/x86 maintainers" , "Dr. David Alan Gilbert" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The guest OS is responsible for protecting itself from intra-guest attacks. The hypervisor can't do that. We want to give the guest OS the tools it needs to make reasonable decisions about the intra-guest protections it wants to enable, in an environment where the virtual processor and the physical processor may not actually have the same F/M/S (and in fact, where the physical processor may change at any time). Right now, we are dealing with one workaround, which is tied to Skylake-era model numbers. Yes, we could report a Skylake model number, and Linux guests would use IBRS instead of retpoline. But this approach doesn't scale. What happens when someone introduces a workaround tied to some other model numbers? On Mon, Jan 29, 2018 at 4:23 PM, Linus Torvalds wrote: > On Mon, Jan 29, 2018 at 1:02 PM, David Woodhouse wrote: >> >> On Mon, 2018-01-29 at 12:44 -0800, Arjan van de Ven wrote: >>> >>> the objective is to have retpoline be safe everywhere and never use IBRS >>> (Linus was also pretty clear about that) so I'm confused by your question > > Note on the unhappiness with some of the patches involved: what I do > *not* want to see is the "on every kernel entry" kind of garbage. > > So my unhappiness with the intel microcode patches is two-fold: > > (a) the interface is nasty and wrong, and I absolutely detest how Intel did it. > > (b) the write to random MSR's on every kernel entry/exit is wrong > > but that doesn't mean that I will necessarily end up NAK'ing every > single IBRS/IBPB patch. > > My concern with (a) is that unlike meltdown, the intel work-around > isn't forward-looking, and doesn't have a "we fixed it" bit. Instead, > it has a "we have a nasty workaround that may or may not be horribly > expensive" bit, and isn't all that well-defined. > > My dislike of (b) comes from "we have retpoline and various wondrous > RSB filling crud already, we're smarter than that". So it's not that I > refuse any IBRS/IBPB use, I refuse the stupid and _mindless_ kind of > use. > >> The question is about all the additional RSB-frobbing and call depth >> counting and other bits that don't really even exist for Skylake yet in >> a coherent form. >> >> If a guest doesn't have those, because it's running some future kernel >> where they *are* implemented but not enabled because at *boot* time it >> discovered it wasn't on Skylake, the question is what happens if that >> guest is subsequently migrated to a Skylake-class machine. > > So I actually have a _different_ question to the virtualization > people. This includes the vmware people, but it also obviously > incldues the Amazon AWS kind of usage. > > When you're a hypervisor (whether vmware or Amazon), why do you even > end up caring about these things so much? You're protected from > meltdown thanks to the virtual environment already having separate > page tables. And the "big hammer" approach to spectre would seem to > be to just make sure the BTB and RSB are flushed at vmexit time - and > even then you might decide that you really want to just move it to > vmenter time, and only do it if the VM has changed since last time > (per CPU). > > Why do you even _care_ about the guest, and how it acts wrt Skylake? > What you should care about is not so much the guests (which do their > own thing) but protect guests from each other, no? > > So I'm a bit mystified by some of this discussion within the context > of virtual machines. I think that is separate from any measures that > the guest machine may then decide to partake in. > > If you are ever going to migrate to Skylake, I think you should just > always tell the guests that you're running on Skylake. That way the > guests will always assume the worst case situation wrt Specte. > > Maybe that mystification comes from me missing something. > > Linus