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[209.132.180.67]) by mx.google.com with ESMTP id h5si1768409pgr.501.2018.01.29.19.33.57; Mon, 29 Jan 2018 19:34:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TYpDA1+6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752743AbeA3DcN (ORCPT + 99 others); Mon, 29 Jan 2018 22:32:13 -0500 Received: from mail-io0-f171.google.com ([209.85.223.171]:35065 "EHLO mail-io0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752661AbeA3DcJ (ORCPT ); Mon, 29 Jan 2018 22:32:09 -0500 Received: by mail-io0-f171.google.com with SMTP id m11so9893353iob.2; Mon, 29 Jan 2018 19:32:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=OLjH14U98GIKxATjgmPTOG2PGVd2iMyddWzqHIxJDkY=; b=TYpDA1+616hZ5CICeCuv9R4rIhMnKdqM03mJ3y7oJbJV1+f050Vn1kuJViV/CGrL2k wglDgtQr8mFntpKYWeKyseCy/FELxcxbUIqGi3qRobayUmojYHKJ1FjhDyd3ogmafzy7 Kb2DOC2v239I7W2URNYplMBo2t4LPBqYZhhOhq9TuaV5ivlY/dFkhqDm45XDGVWUT+hu rdRDVrSPlDB7NIoeaFT89DdY/VBxQ/vucazl2jHw4BR8n1q9ZnWqjci5TZtrXYquOShJ /GYZJp6lS6MuADIrN+MUeN7IQGJpFZKB3uIpRMDpdJUTUO/DWKD/SbU6CIKKW+sUmNNv XkvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=OLjH14U98GIKxATjgmPTOG2PGVd2iMyddWzqHIxJDkY=; b=kfhYJsSNIhRvku5WcpLCfWWW+MGNDMc6dTeijFHzU/S+7PvtJQeI2pcB3gSLrEVuim pto2gvxZIfwlMmv0nsQvgTbASUHZ9JWBbk6A3PoyBbm0AA+FgTrtqI8xlGEcfi64/5Ke NXAk3GZgMhwH79A1uOdW+YJYUxMQt8zafzNvTU4EX8IDrDv/M7qpF+KeDZ0K+KMnpW1s pvmaQEzco+zDtF/1oQbLwkLIp2LLMf0OROWRtWEO5gEMs0HOPAiW7ye/5P8qu9Pmm0aF mk2RCdo2CJF9MaobkIXYXYOPwSWXKEP2Yugl4TZLoN7IeW6OgfQcwKWvfVxOIZtXVzVK a7aw== X-Gm-Message-State: AKwxytdv49KG+YR5JFvf2MvsVCq0Pf1fh2DcgUzJg241FphM23+GI+Cp nk803NKzY1lP2lx/Sf7Pz9w1LBhBzXPG93OngDw= X-Received: by 10.107.81.20 with SMTP id f20mr29223378iob.174.1517283128239; Mon, 29 Jan 2018 19:32:08 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.59.196 with HTTP; Mon, 29 Jan 2018 19:32:06 -0800 (PST) In-Reply-To: <6c024f95-b12c-9c66-91d7-208ed2c380ff@linux.intel.com> References: <1516476182-5153-6-git-send-email-karahmed@amazon.de> <20180129201404.GA1588@localhost.localdomain> <1517257022.18619.30.camel@infradead.org> <20180129204256.GV25150@localhost.localdomain> <31415b7f-9c76-c102-86cd-6bf4e23e3aee@linux.intel.com> <1517259759.18619.38.camel@infradead.org> <6c024f95-b12c-9c66-91d7-208ed2c380ff@linux.intel.com> From: Linus Torvalds Date: Mon, 29 Jan 2018 19:32:06 -0800 X-Google-Sender-Auth: hBazBuzFJb8X9o4kRP6KLPPaAQI Message-ID: Subject: Re: [RFC,05/10] x86/speculation: Add basic IBRS support infrastructure To: Arjan van de Ven Cc: David Woodhouse , Eduardo Habkost , KarimAllah Ahmed , Linux Kernel Mailing List , Andi Kleen , Andrea Arcangeli , Andy Lutomirski , Ashok Raj , Asit Mallick , Borislav Petkov , Dan Williams , Dave Hansen , Greg Kroah-Hartman , "H . Peter Anvin" , Ingo Molnar , Janakarajan Natarajan , Joerg Roedel , Jun Nakajima , Laura Abbott , Masami Hiramatsu , Paolo Bonzini , Peter Zijlstra , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Thomas Gleixner , Tim Chen , Tom Lendacky , KVM list , "the arch/x86 maintainers" , "Dr. David Alan Gilbert" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 29, 2018 at 5:32 PM, Arjan van de Ven wrote: > > the most simple solution is that we set the internal feature bit in Linux > to turn on the "stuff the RSB" workaround is we're on a SKL *or* as a guest > in a VM. That sounds reasonable. However, wouldn't it be even better to extend on the current cpuid model, and actually have some real architectural bits in there. Maybe it could be a bit in that IA32_ARCH_CAPABILITIES MSR. Say, add a bit #2 that says "ret falls back on BTB". Then that bit basically becomes the "Skylake bit". Hmm? Linus