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[209.132.180.67]) by mx.google.com with ESMTP id z96-v6si1548521plh.100.2018.01.30.03.29.03; Tue, 30 Jan 2018 03:29:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@infradead.org header.s=twosheds.20170209 header.b=nWJFUjh8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751561AbeA3L2d (ORCPT + 99 others); Tue, 30 Jan 2018 06:28:33 -0500 Received: from twosheds.infradead.org ([90.155.92.209]:47304 "EHLO twosheds.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751402AbeA3L2c (ORCPT ); Tue, 30 Jan 2018 06:28:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=twosheds.20170209; h=Mime-Version:Date:Content-Type: References:In-Reply-To:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=UzBRcfg8bbiko8gt487oiHyN8KBMjMvsoptpFmoIr60=; b=nWJFUjh8/yu5PdnpAwyO8XhTo MlM7bLTqy2fMdfBI4wPt0Ot3lRrKLBWSAsQuUyvMAq0JDuBGT5+KybwJFQfOB/m0FXUKOHLYKnJba 8nZ+eEBojGPjTL0jmONYcVGB8X+GJMTpqBi3SmXcTM6Tcb50pwXCi1kkSyHj1wUTzRv9REjx0uaNL qDOwToyG+8wBRhXFsS/xSh7rZu9F96Figb4KKfcZlCtOhoN1Wg+lL/qp87lUk9/K7KRNE11+G5wxV WqfXntYQj66BLFlnAUMxpRVHewoyJApMZissXz8etcYJHO8CLFBPvX8aMbQ/cmd7aDtYYOnniSfYh jmmhLZMOQ==; Received: from [2001:8b0:10b:1:c46f:697a:7a7b:515e] by twosheds.infradead.org with esmtpsa (Exim 4.89 #1 (Red Hat Linux)) id 1egU5H-00049H-RQ; Tue, 30 Jan 2018 11:28:20 +0000 Message-ID: <1517311693.18619.102.camel@infradead.org> Subject: Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel From: David Woodhouse To: Borislav Petkov Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org In-Reply-To: <20180130111848.zjv2dngfzcz35lyt@pd.tnic> References: <1517269773-16750-1-git-send-email-dwmw@amazon.co.uk> <20180130105814.m5zd43dyx2o2ius2@pd.tnic> <1517310230.18619.86.camel@infradead.org> <20180130111848.zjv2dngfzcz35lyt@pd.tnic> Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAG1BMVEUHBwcUFBQpKSlGRkZhYWF9fX2Xl5eysrLMzMxFF+rXAAACaElEQVQ4y21UQXbbIBQE9wJALmAg6ToWON22FrhZthHgbvssUPathC7QWMful2JHSmtWwGg+zPxBCE0DU4QoJQgRgsg4w2gJjBNE8PjFBZgnQMBs+uZ1NQNQjZO3BV4AGDFC0f+l4DBG0VUAM4yv7SO8IgRdHXQ+A78HKL5OAeCfNQV5cHX8DsBUyIJKtYbt98BKaGNCKjfgFVkqYVLbkHKsRsbSCSa0T6npIqLrpRBgQKHUpQmgs9eEKaiUcooE8WWfCGVnBiUcn1uF2XhbfmN9apKnmMP2K4kizKkQWxuaVNOpU2cACIyxO1Po8ETHcXEDMVnozcejkAYA9iaD4pU0ZvNQ8VurNnTuFAYVtuIPUZW25PjDIjQAlGyffIiRQxoWAZBmJ0LTdW2Nyc0iP3DqRhxizvGJkBWZmyFVyZkddWzmBoIBVMpCCJ1CFzl98xav4VJKSSD45KbUT75ixikTphDSRh8+Uz7JLgUTAgAFwzqzjxc/nDY7WUApqY0OMdTwCKZSXplSKkgIRCHElCp8ZnhnKqXuwcNbk1L0VXE+I9alUXoHlLHl3mv7/dWQlJwtjREC7mu9L/U2jQyMUuO2EDS4q9Kl2ddm232bxIE5pjJuVwiljNn/Cfv25/T0cu5cZbwHGVq7h/zp0B4n3S99V/utD+Uo8BiGx9xCsOAV5z7/tjo4Z4z1Lvb90KZ7eFOoOeXOukqF2seo234YYuaQPpRP+cVZU5adT1Edun5Iz3z8fTz3+eSDh0Ip1c7zx1MaijGzTd/3MbRuBHz8cvcVgCMBRpOHvgu59WDhoat+nIZm+LWm9C/aaaGq5DCP9QAAAABJRU5ErkJggg== Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-35kCP8+L+/+fCI10ja5t" Date: Tue, 30 Jan 2018 11:28:13 +0000 Mime-Version: 1.0 X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-35kCP8+L+/+fCI10ja5t Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2018-01-30 at 12:18 +0100, Borislav Petkov wrote: > On Tue, Jan 30, 2018 at 11:03:50AM +0000, David Woodhouse wrote: > >=20 > > I pondered that, but I didn't like it. I didn't want to always *force* > > those features on, for all CPUs, just because they happened to be > > discovered at boot time on the first CPU (which *did* have its > > microcode updated by the crappy BIOS, while the others didn't). > >=20 > > I strongly suspect that's purely an academic concern, and we mostly > > check boot_cpu_has() and never even *notice* if secondary CPUs don't > > match. I just didn't want to make that *worse*. It tickled my OCD. > > Well, you need to do it because those bits are AMD-specific and they are > not set in the Intel CPUID leaf and identify_cpu() towards the end takes > care of "ironing" all those bits out which are not part of the common > feature set and which get_cpu_cap() has *not* read out from CPUID. I need to set them for each CPU which has the Intel hardware bits set, sure. I don't need to use setup_force_cpu_cap() to do it. The patch I sent was doing it for each CPU. > It is one of those I-told-you-so moments when I suggested to make the > visible feature bits the artificial ones and have the *actual* hardware > ones set those. We don't have artificial ones for the hardware capability, but yes I could add another three. I could add X86_FEATURE_IBRS which is a virtual bit, set when *either* X86_FEATURE_SPEC_CTRL (on Intel) or X86_FEATURE_AMD_IBRS (on AMD) is set. But actually... that doesn't help, does it? Because early_init_intel() is still only called *once* for the boot CPU. Those software bits would be set... and perhaps not later cleared when identify_boot_cpu() happens later, but would they ever get set for secondary CPUs? The code to set those virtual bits would *still* need to live somewhere that will get called for secondary CPUs, as I've done in this patch. I could use setup_force_cpu_cap() but I still don't like that, as discussed. So no, I don't see why inventing three more "virtual" bits to precisely parallel the AMD bits would really make much difference. --=-35kCP8+L+/+fCI10ja5t Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCEFQw ggUxMIIEGaADAgECAhBNRhEyk/HZ7naOeTHWrzuAMA0GCSqGSIb3DQEBCwUAMIGXMQswCQYDVQQG EwJHQjEbMBkGA1UECBMSR3JlYXRlciBNYW5jaGVzdGVyMRAwDgYDVQQHEwdTYWxmb3JkMRowGAYD VQQKExFDT01PRE8gQ0EgTGltaXRlZDE9MDsGA1UEAxM0Q09NT0RPIFJTQSBDbGllbnQgQXV0aGVu dGljYXRpb24gYW5kIFNlY3VyZSBFbWFpbCBDQTAeFw0xNzEyMjEwMDAwMDBaFw0xODEyMjEyMzU5 NTlaMCQxIjAgBgkqhkiG9w0BCQEWE2R3bXcyQGluZnJhZGVhZC5vcmcwggEiMA0GCSqGSIb3DQEB AQUAA4IBDwAwggEKAoIBAQDgzLNWa18DNpGUj/ZeH0Sgz53ESIbzdPw3OJeuNP6jZhxZojbyfxbM hETscxI/Hj6UZ4a7sHm5BkVjlsB1Af2Za/PXUt8MmLAcPMHkMPGunvkUibEvblDvpqMkQZlaZM+t 5PqFmWkbehLaEvbpNY7dmEAAeKh4klTzJzrr5AAzaCQ32cA2e3+DEIv5O5l9ViMIjy/JM+xMQrfX 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