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[209.132.180.67]) by mx.google.com with ESMTP id v4-v6si1236853ply.828.2018.01.30.03.38.50; Tue, 30 Jan 2018 03:39:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751707AbeA3LhV (ORCPT + 99 others); Tue, 30 Jan 2018 06:37:21 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:44267 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751464AbeA3LhU (ORCPT ); Tue, 30 Jan 2018 06:37:20 -0500 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1egUBB-0005cQ-Gc; Tue, 30 Jan 2018 12:34:21 +0100 Date: Tue, 30 Jan 2018 12:37:10 +0100 (CET) From: Thomas Gleixner To: David Woodhouse cc: Borislav Petkov , arjan@linux.intel.com, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel In-Reply-To: <1517311693.18619.102.camel@infradead.org> Message-ID: References: <1517269773-16750-1-git-send-email-dwmw@amazon.co.uk> <20180130105814.m5zd43dyx2o2ius2@pd.tnic> <1517310230.18619.86.camel@infradead.org> <20180130111848.zjv2dngfzcz35lyt@pd.tnic> <1517311693.18619.102.camel@infradead.org> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 30 Jan 2018, David Woodhouse wrote: > On Tue, 2018-01-30 at 12:18 +0100, Borislav Petkov wrote: > > On Tue, Jan 30, 2018 at 11:03:50AM +0000, David Woodhouse wrote: > > > > > > I pondered that, but I didn't like it. I didn't want to always *force* > > > those features on, for all CPUs, just because they happened to be > > > discovered at boot time on the first CPU (which *did* have its > > > microcode updated by the crappy BIOS, while the others didn't). > > > > > > I strongly suspect that's purely an academic concern, and we mostly > > > check boot_cpu_has() and never even *notice* if secondary CPUs don't > > > match. I just didn't want to make that *worse*. It tickled my OCD. > > > > Well, you need to do it because those bits are AMD-specific and they are > > not set in the Intel CPUID leaf and identify_cpu() towards the end takes > > care of "ironing" all those bits out which are not part of the common > > feature set and which get_cpu_cap() has *not* read out from CPUID. > > I need to set them for each CPU which has the Intel hardware bits set, > sure. I don't need to use setup_force_cpu_cap() to do it. The patch I > sent was doing it for each CPU. > > > It is one of those I-told-you-so moments when I suggested to make the > > visible feature bits the artificial ones and have the *actual* hardware > > ones set those. > > We don't have artificial ones for the hardware capability, but yes I > could add another three. I could add X86_FEATURE_IBRS which is a > virtual bit, set when *either* X86_FEATURE_SPEC_CTRL (on Intel) or > X86_FEATURE_AMD_IBRS (on AMD) is set. > > But actually... that doesn't help, does it? Because early_init_intel() > is still only called *once* for the boot CPU. Those software bits would > be set... and perhaps not later cleared when identify_boot_cpu() > happens later, but would they ever get set for secondary CPUs? The code > to set those virtual bits would *still* need to live somewhere that > will get called for secondary CPUs, as I've done in this patch. > > I could use setup_force_cpu_cap() but I still don't like that, as > discussed. > > So no, I don't see why inventing three more "virtual" bits to precisely > parallel the AMD bits would really make much difference. In any case, if there is ucode mismatch between CPUs the whole thing is hosed anyway no matter what. So can you please agree on a solution so we can unbreak the current state of affairs? Thanks, tglx