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[209.132.180.67]) by mx.google.com with ESMTP id t15si9380941pgq.556.2018.01.30.05.35.26; Tue, 30 Jan 2018 05:35:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752165AbeA3M5b (ORCPT + 99 others); Tue, 30 Jan 2018 07:57:31 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:44348 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752147AbeA3M5a (ORCPT ); Tue, 30 Jan 2018 07:57:30 -0500 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1egVQl-0006qw-Mu; Tue, 30 Jan 2018 13:54:31 +0100 Date: Tue, 30 Jan 2018 13:57:21 +0100 (CET) From: Thomas Gleixner To: David Woodhouse cc: Borislav Petkov , arjan@linux.intel.com, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel In-Reply-To: <1517314193.18619.115.camel@infradead.org> Message-ID: References: <1517269773-16750-1-git-send-email-dwmw@amazon.co.uk> <20180130105814.m5zd43dyx2o2ius2@pd.tnic> <1517310230.18619.86.camel@infradead.org> <20180130111848.zjv2dngfzcz35lyt@pd.tnic> <1517311693.18619.102.camel@infradead.org> <1517314193.18619.115.camel@infradead.org> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323329-632665815-1517317041=:1797" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-632665815-1517317041=:1797 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Tue, 30 Jan 2018, David Woodhouse wrote: > On Tue, 2018-01-30 at 12:37 +0100, Thomas Gleixner wrote: > > > In any case, if there is ucode mismatch between CPUs the whole thing is > > hosed anyway no matter what. So can you please agree on a solution so we > > can unbreak the current state of affairs? > > If there is µcode mismatch between CPUs then the inconsistent bits > should be filtered down to the lowest common denominator and we > shouldn't use the features that are not consistently present. That much > ought to work already with my patch. > > Boris's version uses setup_force_cpu_cap() and forces the bit to be set > even on secondary CPUs which don't really have it, and thus it won't > get filtered out. We'll try to use it, and it will fault on the CPUs > which don't have it. So much for the theory. That's not going to work. If the boot cpu has the feature then the alternatives will have been applied. So even if the flag mismatch can be observed when a secondary CPU comes up the outcome will be access to a non existing MSR and #GP. The whole per cpu feature flag magic in x86 is just an empty shell providing the illusion of supporting heterogenous systems. If that "works" in a particular constellation then by pure chance and not by design. All you can reasonably do is to detect the mismatch once the CPU is brought up and then immediately aborting the hotplug operation _before_ it has the chance to touch anything. But that does not necessarily require per cpu storage. Thanks, tglx --8323329-632665815-1517317041=:1797--