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Date:   Tue, 30 Jan 2018 14:54:17 +0000
From:   Alan Cox <gnomes@lxorguk.ukuu.org.uk>
To:     Arjan van de Ven <arjan@linux.intel.com>
Cc:     Borislav Petkov <bp@alien8.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        David Woodhouse <dwmw2@infradead.org>, karahmed@amazon.de,
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        pbonzini@redhat.com, ak@linux.intel.com,
        torvalds@linux-foundation.org, gregkh@linux-foundation.org
Subject: Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature
 bits on Intel
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On Tue, 30 Jan 2018 06:01:43 -0800
Arjan van de Ven <arjan@linux.intel.com> wrote:

> On 1/30/2018 5:11 AM, Borislav Petkov wrote:
> > On Tue, Jan 30, 2018 at 01:57:21PM +0100, Thomas Gleixner wrote:  
> >> So much for the theory. That's not going to work. If the boot cpu has the
> >> feature then the alternatives will have been applied. So even if the flag
> >> mismatch can be observed when a secondary CPU comes up the outcome will be
> >> access to a non existing MSR and #GP.  
> > 
> > Yes, with mismatched microcode we're f*cked.  
> 
> I think in the super early days of SMP there was an occasional broken BIOS.
> (and when Linux then did the ucode update it was sane again)
> 
> Not since a long time though (I think the various certification suites check for it now)

The only case I can think of where you'd get a non boot processor that
didn't have the same microcode loaded as the rest on entry to the OS would
be in a system where it was possibly to phyically hot plug processors
post boot.

There are not many such systems and it may be that all of them do
sufficient deeply unmentionable things in their firmware to cover this.

Alan