Received: by 10.223.176.5 with SMTP id f5csp1218863wra; Wed, 31 Jan 2018 03:09:41 -0800 (PST) X-Google-Smtp-Source: AH8x227mNkofXeC/wy1X7fnLXUuDGTmjApExriVVQGSpUiw1vioYbi8JAkoay2a5ZimF2NWYoVPQ X-Received: by 2002:a17:902:9a84:: with SMTP id w4-v6mr15401692plp.136.1517396980950; Wed, 31 Jan 2018 03:09:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517396980; cv=none; d=google.com; s=arc-20160816; b=JjzwVse4lMM8RFc9jCY/+b6vYdmroNjsRLxWjWAhBHlUtsDWJxFbJZbxHIudsP0BQS 8xi9zsxTwY6YwSxNt+ySVD8z2GU7YL4qUoxnzagOmQIVnlxMnffVjTa5dheUHb4C/L7y zz9SlZJSaZf3fpVuCoH8VHfvw08LbiD4P9gaM52ArGy84wXFOTzSMCQZjZUBgYJuFEBZ 6l+ptMMeb8/i86S0yhg+Rkwml3Z8nilFf9Mx0kYdSfe2wP6zTIggmWTD1mn0DZMT22gv XVvDML8w7RaLC/OoB/yFbAFFRU4D29Rdx0zWOxmeoMh/uY6e+ZvVZH8Xd0DnOcbGZ5f3 I33A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dmarc-filter:dkim-signature:dkim-signature :arc-authentication-results; bh=KHMZpJKSCPXidKRtBBGHoSb+ihuZ2b87rha5/wP5auw=; b=JW1Pe3nUdJd/kY1ZSS+mggmUxxintYf6ZtX5iig1D4e3tpymfz/FPlGQBhI0+SeM65 rocpAU9jDAS7RwFoTTngawB4134L2uzMjvCrOci2M3U4Kqh0vlSP+J45c+MJ9sCE9xVx Y1zUp+AMFuR47OQdEfHDTjBq2CH+mCmXQ5izN/1uWqPXDDyehUQMcZjzOP5i96PsaLO7 rRJXctQpK1/zFqe7IFpbhTPXmt0I5DgA6kwbbjvYVe4Dv6NrbGZSqD6hzlQ97/w6W+bb lwSGwAJ9Nk36Urnr2WwUzpxfsLiVlWHCt2jtjQ5rCIRQgs6vFRtWZNjhWo9uvHcZdBOG OSog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=hIxc0ssZ; dkim=pass header.i=@codeaurora.org header.s=default header.b=hIxc0ssZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n3-v6si4468108pld.150.2018.01.31.03.09.26; Wed, 31 Jan 2018 03:09:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=hIxc0ssZ; dkim=pass header.i=@codeaurora.org header.s=default header.b=hIxc0ssZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753148AbeAaKzr (ORCPT + 99 others); Wed, 31 Jan 2018 05:55:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:40554 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752366AbeAaKzp (ORCPT ); Wed, 31 Jan 2018 05:55:45 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D90FE6050D; Wed, 31 Jan 2018 10:55:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517396144; bh=CUBU9eIYf8TW1d1ZQl1P317PUt7H3Quc7hP4AdgQFCo=; h=From:To:Cc:Subject:Date:From; b=hIxc0ssZTnqEZL2qz697YHUDHuEVEZ40raedU8CN1TjqoUxsD0IJSvcaN9CI/x1zi hFRYGHuzg9G8nvTpN239QkuVxIex+zBeJkcKggmItJOiErEpDIhIiKACWv3u3eetZk nEOIeclh1wnHW5RbBKjXRd4mmz36VxUxJULflgfI= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 77B026050D; Wed, 31 Jan 2018 10:55:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517396144; bh=CUBU9eIYf8TW1d1ZQl1P317PUt7H3Quc7hP4AdgQFCo=; h=From:To:Cc:Subject:Date:From; b=hIxc0ssZTnqEZL2qz697YHUDHuEVEZ40raedU8CN1TjqoUxsD0IJSvcaN9CI/x1zi hFRYGHuzg9G8nvTpN239QkuVxIex+zBeJkcKggmItJOiErEpDIhIiKACWv3u3eetZk nEOIeclh1wnHW5RbBKjXRd4mmz36VxUxJULflgfI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 77B026050D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH 0/4] Misc patches to support clocks for SDM845 Date: Wed, 31 Jan 2018 16:24:31 +0530 Message-Id: <1517396075-29297-1-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series does the miscellaneous changes to support clock nodes for SDM845. Below are the major changes for which the existing code does not have support. 1. Clear hardware clock control bit of RCGs where HW clock control bit is set by default so that software can control those root clocks. 2. Introduces clk_rcg2_shared_ops to support clock controller drivers for SDM845. With new shared ops, RCGs with shared branches will be configured to a safe source in disable path and actual RCG update configuration will be done in enable path instead of doing config update in set_rate. In set_rate(), just cache the rate instead of doing actual configuration update. Also each RCG in clock controller driver will have their own safe configuration frequency table to switch to safe frequency. 3. Add support for controlling Fabia PLL for which the support is not available in existing alpha PLL code. 4. Add Global Clock controller (GCC) driver for SDM845. This should allow most non-multimedia device drivers to probe and control their clocks. Amit Nischal (3): clk: qcom: Clear hardware clock control bit of RCG clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for controlling Fabia PLL Taniya Das (1): clk: qcom: Add Global Clock controller (GCC) driver for SDM845 .../devicetree/bindings/clock/qcom,gcc.txt | 1 + drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 322 +- drivers/clk/qcom/clk-alpha-pll.h | 16 + drivers/clk/qcom/clk-rcg.h | 8 +- drivers/clk/qcom/clk-rcg2.c | 154 +- drivers/clk/qcom/gcc-sdm845.c | 3619 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 242 ++ 9 files changed, 4365 insertions(+), 9 deletions(-) create mode 100644 drivers/clk/qcom/gcc-sdm845.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation